Semiconductor devices having different impurity regions in active pattern

Patent metadata

Field	Value
Publication number	US-12501673-B2
Application number	US-202318196081-A
Country	US
Kind code	B2
Filing date	May 11, 2023
Priority date	Jul 4, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A semiconductor device include first and second active patterns, first and second gate structures, and first and second source/drain layers. The first and second active patterns extend on the first and second regions in a first direction. The first and second gate structures are formed on the first and second active patterns, and extend in a second direction. The first and second source/drain layers are formed on the first and second active patterns adjacent to the first and second gate structures. The first active pattern includes a first well having first and second impurity regions. The second active pattern includes a second well having third and fourth impurity regions. A width in the second direction of the first impurity region is greater than that of the second impurity region. A width in the second direction of the third impurity region is smaller than that of the fourth impurity region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
first and second active patterns on a substrate including first and second regions, the first and second active patterns extending on the first and second regions, respectively, of the substrate in a first direction substantially parallel to an upper surface of the substrate; first and second gate structures on the first and second active patterns, respectively, the first and second gate structures extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; and first and second source/drain layers on portions of the first and second active patterns, respectively, adjacent to the first and second gate structures, respectively, wherein the first active pattern comprises a first well having first and second impurity regions stacked in a third direction substantially perpendicular to the first and second directions, wherein the second active pattern comprises a second well having third and fourth impurity regions stacked in the third direction, wherein a width in the second direction of the first impurity region is greater than a width in the second direction of the second impurity region, and wherein a width in the second direction of the third impurity region is smaller than a width in the second direction of the fourth impurity region.

2 . The semiconductor device of claim 1 , wherein the first impurity region is formed at a portion of the substrate under the first active pattern, and
wherein a maximum width in the second direction of the first impurity region is greater than a width in the second direction of the first active pattern.

3 . The semiconductor device of claim 1 , wherein the width in the second direction of the second impurity region is smaller than a width in the second direction of the first active pattern.

4 . The semiconductor device of claim 1 , wherein the width in the second direction of the third impurity region is smaller than a width in the second direction of the second active pattern, and the width in the second direction of the fourth impurity region is substantially equal to the width in the second direction of the second active pattern.

5 . The semiconductor device of claim 1 , wherein an impurity concentration of the first impurity region is greater than an impurity concentration of the second impurity region, and an impurity concentration of the third impurity region is smaller than an impurity concentration of the fourth impurity region.

6 . The semiconductor device of claim 1 , wherein the first and second impurity regions comprise one or more n-type impurities, and the third and fourth impurity regions comprise one or more p-type impurities.

7 . The semiconductor device of claim 6 , wherein the first source/drain layer comprises silicon-germanium doped with one or more p-type impurities, and the second source/drain layer comprises silicon doped with one or more n-type impurities or silicon carbide doped with one or more n-type impurities.

8 . The semiconductor device of claim 1 , wherein the first well further comprises a fifth impurity region between the first and second impurity regions, and the second well further comprises a sixth impurity region between the third and fourth impurity regions,
wherein a width in the second direction of the fifth impurity region is substantially equal to a width in the second direction of the first active pattern, and a width in the second direction of the sixth impurity region is smaller than a width in the second direction of the second active pattern.

9 . The semiconductor device of claim 8 , wherein an impurity concentration of the fifth impurity region is greater than an impurity concentration of the second impurity region, and an impurity concentration of the sixth impurity region is smaller than an impurity concentration of the fourth impurity region.

10 . The semiconductor device of claim 1 , further comprising:
first channels spaced apart from each other in the third direction, each of the first channels extending in the first direction through the first gate structure; and second channels spaced apart from each other in the third direction, each of the second channels extending in the first direction through the second gate structure.

11 . The semiconductor device of claim 10 , further comprising an inner spacer between the second source/drain layer and a portion of the second gate structure between the second channels.

12 . A semiconductor device, comprising:
an active pattern on a substrate, the active pattern extending in a first direction substantially parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other in a third direction substantially perpendicular to the first and second directions, each of the channels extending in the first direction through the gate structure; and a source/drain layer on a portion of the active pattern adjacent to the gate structure, wherein the substrate and the active pattern comprise a well having first, second and third impurity regions stacked in the third direction, wherein a maximum width in the second direction of the first impurity region is greater than a width in the second direction of the active pattern, wherein a width in the second direction of the second impurity region is substantially equal to the width in the second direction of the active pattern, and wherein a width in the second direction of the third impurity region is smaller than the width in the second direction of the active pattern.

13 . The semiconductor device of claim 12 , wherein an impurity concentration of each of the first and second impurity regions is greater than an impurity concentration of the third impurity region.

14 . The semiconductor device of claim 12 , wherein each of the first to third impurity regions comprises one or more n-type impurities.

15 . The semiconductor device of claim 14 , wherein the source/drain layer comprises silicon-germanium doped with one or more p-type impurities.

16 . A semiconductor device, comprising:
an active pattern on a substrate, the active pattern extending in a first direction substantially parallel to an upper surface of the substrate; a gate structure on the active pattern, the gate structure extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction; channels spaced apart from each other in a third direction substantially perpendicular to the first and second direction, each of the channels extending in the first direction through the gate structure; and a source/drain layer on a portion of the active pattern adjacent to the gate structure, wherein the substrate and the active pattern comprise a well having first, second and third impurity regions stacked in the third direction, wherein a width in the second direction of each of the first and second impurity region is smaller than a width in the second direction of the active pattern, and wherein a width in the second direction of the third impurity region is substantially equal to the width in the second direction of the active pattern.

17 . The semiconductor device of claim 16 , wherein an impurity concentration of each of the first and second impurity regions is smaller than an impurity concentration of the third impurity r

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Seokhyeon
• Kim Taehyeon
• Lee Seunghun
• Kim Hyeongrae

Classifications

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D62/121 Primary

  oriented parallel to substrates · CPC title