MOSFET devices with asymmetric structural configurations introducing different electrical characteristics

Patent metadata

Field	Value
Publication number	US-9837320-B2
Application number	US-201715582962-A
Country	US
Kind code	B2
Filing date	May 1, 2017
Priority date	Jun 30, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.

First claim

What is claimed is:

1. A method for fabricating transistors in a semiconductor substrate layer having a first conductivity-type dopant at a first dopant concentration level, the semiconductor substrate layer including a first region and a second region, comprising:
forming a gate region extending over the first and second regions;
implanting first conductivity-type dopant in the first region, but not the second region, of the semiconductor substrate layer to form a well implant;
implanting second conductivity-type dopant in the well implant in the first region and in the semiconductor substrate layer in the second region to form a first body implant in the first region and a second body implant in the second region;
annealing to activate and diffuse the first and second conductivity-type dopants to form a well region in the semiconductor substrate layer from the well implant having a second dopant concentration level greater than the first dopant concentration level, a first body region in the well region from the first body implant and a second body region in the semiconductor substrate layer from the second body implant;
implanting first conductivity-type dopant in the first body region to form a first source implant and in the second body region for form a second source implant; and
annealing to activate and diffuse the first conductivity-type dopants of the first and second source implants to form first and second source regions.

2. The method of claim 1 , wherein implanting second conductivity-type dopant in the well implant and in the semiconductor substrate layer to form the first and second body implants comprises using the gate region as an implantation mask.

3. The method of claim 1 , further comprising:
forming a hard mask on the semiconductor substrate layer which includes an oxide layer and a nitride layer;
opening a first opening through the nitride layer in the first region; and
opening a second opening through the nitride layer in the second region.

4. The method of claim 3 , wherein implanting the first conductivity-type dopant in the first region to form the well implant comprises implanting through the first opening but not the second opening.

5. The method of claim 3 , wherein forming the gate region comprises:
conformally depositing a layer of polysilicon over the nitride layer and oxide layer in the first and second openings; and
forming third openings in the layer of polysilicon within the first and second openings.

6. The method of claim 5 , wherein implanting second conductivity-type dopant in the well implant and in the semiconductor substrate layer to form the first and second body implants comprises implanting through the third openings in the layer of polysilicon.

7. The method of claim 6 , further comprising:
forming a source implant mask in each of the third openings; and
wherein implanting the first conductivity-type dopant in the well region and in the second body region for form the first and second source implants comprises implanting using the source implant mask and gate region as an implantation mask.

8. The method of claim 1 , wherein the first source region is laterally offset from the well region by a first channel having a first length and the second source region is laterally offset from material of the semiconductor substrate layer by a second channel having a second length greater than the first length.

9. The method of claim 8 , wherein the second length exceeds the first length by a lateral thickness of the well region.

10. The method of claim 1 , wherein the first body region and first source region are associated with a first transistor, and wherein the second body region and second source region are associated with a second transistor, and wherein the first and second transistors have different electrical characteristics.

11. The method of claim 10 , wherein an electrical characteristic which is different is selected from the group consisting of zero temperature coefficient, on resistance, threshold voltage and transconductance.

12. A method for fabricating an integrated circuit on a semiconductor substrate layer having a first conductivity-type dopant at a first dopant concentration level, the semiconductor substrate layer including a first region and a second region, comprising:
forming a well region within and in contact with the first region of the semiconductor substrate layer, said well region having the first conductivity-type dopant at a second dopant concentration level greater than the first dopant concentration level;
forming a first body region within and in contact with the well region having a second conductivity-type dopant;
forming a second body region within and in contact with the semiconductor substrate layer at the second region also having the second conductivity-type dopant;
forming a first source region within and in contact with the first body region at a position that is laterally offset from the well region by a first channel region having a first length;
forming a second source region within and in contact with the second body region at a position that is laterally offset from material of the semiconductor substrate layer by a second channel region having a second length greater than the first length; and
forming a gate region extending over both the first and second channel regions.

13. The method of claim 12 , wherein forming the first and second body regions comprises using the gate region as an implantation mask for implanting the second conductivity-type dopant.

14. The method of claim 13 , wherein:
forming the well region comprises implanting the first conductivity-type dopant; and
further comprising annealing to activate and diffuse the implanted first and second conductivity-type dopants to produce the well region and the first and second body regions.

15. The method of claim 12 , wherein the first source region is laterally offset from the well region by a first channel having a first length and the second source region is laterally offset from material of the semiconductor substrate layer by a second channel having a second length greater than the first length.

16. The method of claim 15 , wherein the second length exceeds the first length by a lateral thickness of the well region.

Assignees

• St Microelectronics Inc

Inventors

• Pritiskutch John C
• Hildenbrandt Richard

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title