FinFET structure and method for manufacturing thereof

Patent metadata

Field	Value
Publication number	US-9806154-B2
Application number	US-201514600781-A
Country	US
Kind code	B2
Filing date	Jan 20, 2015
Priority date	Jan 20, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm 3 . The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm 3 . The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm 3 .

First claim

What is claimed is:

1. A FinFET structure, comprising:
a substrate;
a fin protruding from the substrate;
a gate surrounding a first portion of the fin; and
an insulating layer surrounding a second portion of the fin, the first portion overlying the second portion;
wherein a dopant concentration in a lower portion of the insulating layer is greater than a dopant concentration in an upper portion of the insulating layer, the lower portion is in direct contact with the substrate.

2. The FinFET structure of claim 1 , wherein the dopant concentration of the second portion of the fin is greater than about 5E18/cm 3 .

3. The FinFET structure of claim 1 , wherein the lower portion of the insulating layer has a dopant concentration greater than about 1E19/cm 3 .

4. The FinFET structure of claim 1 , wherein the upper portion of the insulating layer is essentially dopant-free.

5. The FinFET structure of claim 2 , wherein the second portion of the fin further comprises a heavier doped region in proximity to an interface of the first portion and the second portion of the fin, dopant concentrations at a top and a bottom of the heavier doped region being substantially identical.

6. The FinFET structure of claim 5 , the dopant concentration of the heavier doped region is greater than about 1E19/cm 3 .

7. The FinFET structure of claim 5 , wherein the second portion of the fin further comprises a lighter doped region below the heavier doped region, dopant concentration at a top and a bottom of the lighter doped region being substantially identical.

8. A MOS structure, comprising:
a substrate;
a fin protruding from the substrate; and
an insulating layer surrounding a well portion of the fin, a channel portion of the fin extruding from the insulating layer,
wherein a dopant concentration in an upper portion of the insulating layer is lower than a dopant concentration in a lower portion of the insulating layer, and
wherein the lower portion of the insulating layer is in direct contact with the substrate.

9. The MOS structure of claim 8 , wherein the upper portion is essentially dopant-free.

10. The MOS structure of claim 8 , wherein the channel portion is surrounded by a metal gate, a dopant concentration of the channel portion is essentially identical to the dopant concentration of the substrate.

11. The MOS structure of claim 8 , wherein the dopant concentration of the well portion is greater than about 5E18/cm 3 .

12. The MOS structure of claim 10 , wherein the well portion further comprises an anti-punch through region in proximity to the channel portion, a concentration difference between a top and a bottom of the anti-punch through region is less than about 3%.

13. The MOS structure of claim 8 , wherein the upper portion and the lower portion of the insulating layer are two layers having an interface therebetween.

14. A semiconductor structure, comprising:
a substrate;
a fin on the substrate; and
an insulating layer surrounding a well portion of the fin, a channel portion of the fin extruding from the insulating layer;
wherein a dopant concentration in a lower layer of the insulating layer is greater than a dopant concentration in an upper layer of the insulating layer, the lower layer is in direct contact with the substrate.

15. The semiconductor structure of claim 14 , wherein the lower layer has a dopant concentration greater than about 1E19/cm 3 .

16. The semiconductor structure of claim 14 , wherein the upper layer is essentially dopant-free.

17. The semiconductor structure of claim 16 , wherein the upper layer and the lower layer of the insulating layer are two layers having an interface therebetween.

18. The semiconductor structure of claim 14 , wherein an upper portion of the well portion comprises a dopant concentration of greater than about 1E19/cm 3 .

19. The semiconductor structure of claim 18 , wherein a dopant concentration difference between the upper portion and a lower portion of the well portion is less than about 3%.

20. The semiconductor structure of claim 14 , wherein a lower portion of the well portion comprises a lower dopant concentration than a dopant concentration of an upper portion of the well portion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Chun Hsiung
• Chong Lai-Wan
• Lee Chien-Wei
• Chen Kei-Wei

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H01L29/1083

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L29/66803

  Electricity · mapped topic