FinFETs with strained well regions

Patent metadata

Field	Value
Publication number	US-9859380-B2
Application number	US-201715450201-A
Country	US
Kind code	B2
Filing date	Mar 6, 2017
Priority date	Feb 27, 2013
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

First claim

What is claimed is:

1. A device comprising:
a substrate;
isolation regions over a portion of the substrate;
a semiconductor region having a tensile strain, wherein the semiconductor region comprises:
a wide portion having sidewalls contacting the isolation regions; and
a narrow portion narrower than the wide portion, wherein the narrow portion is higher than top surfaces of the isolation regions to form a semiconductor fin;

a gate stack comprising a gate dielectric, wherein the gate dielectric extends on a top surface and a sidewall of the semiconductor fin; and
a source region and a drain region on opposite sides of the gate stack, wherein both the wide portion and the narrow portion extend from the source region to the drain region.

2. The device of claim 1 further comprising:
a relaxed semiconductor region between the isolation regions and having a first conduction band, wherein the semiconductor fin has a second conduction band lower than the first conduction band.

3. The device of claim 1 further comprising a first semiconductor layer contacting the top surface and the sidewalls of the semiconductor fin, wherein the first semiconductor layer is substantially free from p-type and n-type impurities.

4. The device of claim 3 further comprising a second semiconductor layer over and contacting the first semiconductor layer, wherein the second semiconductor layer comprises an n-type impurity.

5. The device of claim 4 further comprising a third semiconductor layer over and contacting the second semiconductor layer, wherein the third semiconductor layer is substantially free from n-type impurities.

6. The device of claim 4 , wherein both the first semiconductor layer and the second semiconductor layer comprise silicon and germanium, and the first semiconductor layer and the second semiconductor layer have substantially a same germanium percentage.

7. The device of claim 1 further comprising a silicon cap between the semiconductor fin and the gate stack, wherein the silicon cap is free from n-type impurities.

8. A device comprising:
a silicon substrate;
Shallow Trench Isolation (STI) regions extending into a portion of the silicon substrate;
a silicon germanium region comprising:
a wide portion having a first sidewall and a top surface, wherein the first sidewall contacts a sidewall of the STI regions; and
a narrow portion over the wide portion and having a second sidewall, wherein the first sidewall and the second sidewall are on a same side of the silicon germanium region, and wherein the top surface of the wide portion connects the first sidewall to the second sidewall;

a first silicon germanium layer on a top surface and sidewalls of the narrow portion;
a second silicon germanium layer over and contacting the first silicon germanium layer, wherein the first and the second silicon germanium layers have higher germanium percentages than the silicon germanium region, and the second silicon germanium layer has an n-type impurity concentration higher than the first silicon germanium layer;
a gate dielectric over the second silicon germanium layer; and
a gate electrode over the gate dielectric.

9. The device of claim 8 further comprising a source region and a drain region on opposite ends of the silicon germanium region, wherein the source region and the drain region are doped with an n-type impurity, and the first silicon germanium layer is free from n-type impurities.

10. The device of claim 9 , wherein the first silicon germanium layer is further free from p-type impurities.

11. The device of claim 8 further comprising a source region and a drain region on opposite sides of the gate dielectric and the gate electrode, wherein the second sidewall extends from the source region to the drain region.

12. The device of claim 8 further comprising a third silicon germanium layer over and contacting the second silicon germanium layer, wherein the third silicon germanium layer has a lower n-type impurity concentration than the second silicon germanium layer.

13. The device of claim 12 , wherein the third silicon germanium layer is free from n-type impurities.

14. The device of claim 12 , wherein the second silicon germanium layer has a conduction band lower than conduction bands of the first silicon germanium layer and the third silicon germanium layer.

15. A device comprising:
a silicon substrate;
Shallow Trench Isolation (STI) regions extending into a portion of the silicon substrate;
a first silicon germanium (SiGe) region located between and in contact with the STI regions, wherein the first SiGe region has a first germanium atomic percentage;
a second SiGe region over and in contact with the first SiGe region, wherein the second SiGe region has a second germanium atomic percentage higher than the first silicon germanium region;
a third SiGe region contacting a top surface and sidewalls of an upper portion of second SiGe region, wherein the third SiGe region comprises:
a first SiGe layer not doped with either of n-type and p-type impurities; and
a second SiGe layer doped with an n-type impurity over the first SiGe layer;

a gate dielectric over the third SiGe region;
a gate electrode over the gate dielectric; and
a source region and a drain region on opposite sides of the gate dielectric and the gate electrode.

16. The device of claim 15 , wherein the second SiGe region extends from the source region to the drain region.

17. The device of claim 15 , wherein the first SiGe layer is un-doped with n-type impurities.

18. The device of claim 17 , wherein the first SiGe layer is further un-doped with p-type impurities.

19. The device of claim 17 , wherein the third SiGe region further comprises a third SiGe layer over the second SiGe layer, wherein the third SiGe layer is free from n-type impurities.

20. The device of claim 19 , further comprising a silicon cap over the third SiGe layer, wherein the silicon cap is neither doped with n-type impurities nor doped with p-type impurities.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yi-Jing
• Liu Chi-Wen
• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/3438

  Doping during depositing · CPC title