Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12501607-B2
Application number	US-202217741701-A
Country	US
Kind code	B2
Filing date	May 11, 2022
Priority date	Aug 17, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a peripheral circuit structure including:
peripheral circuits on a semiconductor substrate, and
a lower insulating layer covering the peripheral circuits;
a plurality of bit lines extending in a first direction on the peripheral circuit structure; a mold insulating pattern having trenches, the mold insulating pattern extending in a second direction to cross the plurality of bit lines; a first word line and a second word line in each of the trenches, the first word line and the second word line extending in the second direction to cross the plurality of bit lines; a plurality of channel patterns between the plurality of bit lines and each of the first word line and the second word lines, each channel pattern of the plurality of channel patterns including:
a first vertical channel portion and a second vertical channel portions spaced apart from each other in a third direction, the third direction being inclined with respect to the first direction and the second directions, and
a horizontal channel portion connecting the first vertical channel portion and the second vertical channel portions to each other;
a gate insulating pattern between the plurality of channel patterns and each of the first word line and the second word lines, the gate insulating pattern extending in the second direction; a pair of landing pads connected to the first vertical channel portion and the second vertical channel portions of each channel pattern of the plurality of channel patterns, respectively; and a pair of data storage patterns on the pair of landing pads, respectively.

2 . The semiconductor memory device as claimed in claim 1 ,
wherein the plurality of channel patterns are spaced apart from each other in the second direction and the third directions.

3 . The semiconductor memory device as claimed in claim 1 ,
wherein the horizontal channel portion of each channel pattern of the plurality of channel patterns is in contact with a portion of a top surface of a corresponding bit line of the plurality of bit lines.

4 . The semiconductor memory device as claimed in claim 1 ,
wherein a portion of the horizontal channel portion of each channel pattern of the plurality of channel patterns is between the first word line and the second word lines.

5 . The semiconductor memory device as claimed in claim 1 , wherein:
each of the trenches has a first width in the first direction, and each of the first word line and the second word lines has a second width smaller than half the first width in the first direction.

6 . The semiconductor memory device as claimed in claim 1 ,
wherein a distance between the pair of the data storage patterns, which are adjacent to each other in the second direction, is substantially equal to a distance between the pair of the data storage patterns, which are adjacent to each other in the third direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kiseok
• Kim Keunnam
• Kim Hui-Jung
• Lee Wonsok
• Cho Min Hee

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title