Non-volatile memory cell with self aligned floating and erase gates, and method of making same

Patent metadata

Field	Value
Publication number	US-9293204-B2
Application number	US-201414252929-A
Country	US
Kind code	B2
Filing date	Apr 15, 2014
Priority date	Apr 16, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.

First claim

What is claimed is:

1. A pair of memory cells, comprising:
a substrate of semiconductor material having a first conductivity type and a surface;
a trench formed into the surface of the substrate and including a pair of opposing sidewalls;
a first region formed in the substrate under the trench;
a pair of second regions formed in the substrate, with a pair of channel regions each in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the substrate surface;
a pair of electrically conductive floating gates each at least partially disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion, and over and insulated from the first region;
an electrically conductive erase gate having a lower portion disposed in the trench and disposed adjacent to and insulated from the floating gates;
an electrically conductive coupling gate disposed in the trench, disposed between and insulated from the floating gates, disposed over and insulated from the first region, and disposed under and insulated from the erase gate; and
a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion.

2. The pair of memory cells of claim 1 , wherein the coupling gate is insulated from the first region by thicker insulation material than are the floating gates.

3. The pair of memory cells of claim 1 , wherein:
the coupling gate is insulated from the first region by insulation material having a total first thickness;
the floating gates are insulated from the first region by insulation material having a total second thickness; and
the first thickness is greater than the second thickness.

4. The pair of memory cells of claim 1 , wherein there is no vertical overlap between the pair of control gates and the pair of floating gates.

5. The pair of memory cells of claim 1 , wherein the erase gate is disposed adjacent to the floating gates and insulated therefrom with insulation material having a thickness that permits Fowler-Nordheim tunneling.

6. The pair of memory cells of claim 1 , wherein the erase gate includes a pair of notches and each of the floating gates includes an edge that directly faces and is insulated from one of the pair of notches.

7. The pair of memory cells of claim 6 , wherein the erase gate includes an upper portion having a first width, and wherein the erase gate lower portion has a second width that is less than the first width.

8. The pair of memory cells of claim 7 , wherein the pair of notches are disposed where the upper and lower portions of the erase gate meet.

9. A method of forming a pair of memory cells, comprising:
forming a trench into a surface of the semiconductor substrate of first conductivity type, wherein the trench has a pair of opposing sidewalls;
forming a first region in the substrate and under the trench;
forming a pair of second regions in the substrate, with a pair of channel regions each defined in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the surface of the substrate;
forming a pair of electrically conductive floating gates each at least partially disposed in the trench adjacent to and insulated from one of the channel region first portions for controlling a conductivity of the one channel region first portion;
forming an electrically conductive erase gate having a lower portion disposed in the trench and disposed adjacent to and insulated from the floating gates;
forming an electrically conductive coupling gate disposed in the trench, disposed between and insulated from the floating gates, disposed over and insulated from the first region, and disposed under and insulated from the erase gate; and
forming a pair of electrically conductive control gates each disposed over and insulated from one of the channel region second portions for controlling a conductivity of the one channel region second portion.

10. The method of claim 9 , wherein the coupling gate is insulated from the first region by thicker insulation material than are the floating gates.

11. The method of claim 9 , wherein:
the coupling gate is insulated from the first region by insulation material having a total first thickness;
the floating gates are insulated from the first region by insulation material having a total second thickness; and
the first thickness is greater than the second thickness.

12. The method of claim 9 , wherein there is no vertical overlap between the pair of control gates and the pair of floating gates.

13. The method of claim 9 , wherein the erase gate includes a pair of notches and each of the floating gates includes an edge that directly faces and is insulated from one of the pair of notches.

14. The method of claim 13 , wherein the formation of the erase gate comprises:
forming an upper portion of the erase gate having a first width; and
forming the lower portion of the erase gate having a second width that is less than the first width.

15. The method of claim 14 , wherein the pair of notches are disposed where the upper and lower portions of the erase gate meet.

16. The method of claim 9 , further comprising:
forming a sacrificial layer of oxide on the opposing sidewalls of the trench; and
removing the sacrificial layer of oxide.

17. The method of claim 9 , wherein the formation of the floating gates comprises:
forming conductive material in the trench;
forming a pair of opposing spacers of insulation material on the conductive material such that a portion of the conductive material is exposed between the pair of opposing spacers; and
removing the exposed portion of the conductive material.

18. The method of claim 17 , wherein the removing of the exposed portion of the conductive material comprises an anisotropic etch.

19. The method of claim 17 , wherein the formation of the erase and control gates comprises:
forming a layer of conductive material having a first portion disposed between the opposing spacers, and second and third portions disposed over the substrate surface with the opposing spacers disposed there between.

20. A method of programming one of a pair of memory cells, whereby the pair of memory cells comprise a substrate of semiconductor material having a first conductivity type and a surface, a trench formed into the surface of the substrate and including a pair of opposing sidewalls, a first region formed in the substrate under the trench, a pair of second regions formed in the substrate, with a pair of channel regions each in the substrate between the first region and one of the second regions, wherein the first and second regions have a second conductivity type, and wherein each of the channel regions includes a first portion that extends substantially along one of the opposing trench sidewalls and a second portion that extends substantially along the substrate surface, a pair

Assignees

• Silicon Storage Tech Inc

Inventors

• Do Nhan
• Kim Jinho
• Liu Xian

Classifications

• G11C16/0416

  comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H10D30/6894

  having one gate at least partly in a trench · CPC title

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title