Substrate and semiconductor package

Patent metadata

Field	Value
Publication number	US-12500182-B2
Application number	US-202017759344-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	Jan 31, 2020
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

Damage to a joint part of a terminal of an electronic component mounted on a substrate is detected. The substrate includes a base material unit, a land, and a light detection unit. The land included in the substrate is arranged with a stress light emitting body configured to emit light in accordance with stress, includes a transparent member, and is joined with a terminal of an element arranged in the base material unit included in the substrate. The light detection unit included in the substrate is arranged between the base material unit and the land included in the substrate, and detects light from the stress light emitting body.

First claim

The invention claimed is:

1 . A substrate, comprising:
a base material unit; a first land that includes:
a stress light emitting body configured to emit light based on stress between the substrate and an element; and
a transparent member joined with a terminal of the element;
a light detection unit between the base material unit and the first land, wherein the light detection unit is configured to detect the light from the stress light emitting body; a stress detection unit that includes a damage detection unit, wherein the stress detection unit is configured to detect the stress in the first land based on a first detection result of the detection of the light by the light detection unit; and the damage detection unit configured to detect damage of a joint part between the terminal and the first land based on the detected stress.

2 . The substrate according to claim 1 , further comprising a plurality of lands that includes the first land, wherein
the plurality of lands is connected to a plurality of terminals of the element, and the plurality of terminals includes the terminal.

3 . The substrate according to claim 1 , wherein
the first land is at a corner of the substrate, the terminal is at a corner of the element, and the terminal, joined to the first land at the corner of the substrate, has a wiring structure not having a function as a signal line through which an electric signal passes between inside and outside of the element.

4 . The substrate according to claim 1 , wherein the light detection unit is further configured to output an electric signal based on the detected light.

5 . The substrate according to claim 1 , wherein the stress detection unit is further configured to:
compare the first detection result of the light detection unit with a threshold value; and detect the stress based on the comparison.

6 . The substrate according to claim 1 , wherein the stress detection unit is further configured to detect the stress based on a change in the first detection result of the light detection unit.

7 . The substrate according to claim 6 , wherein
the stress detection unit further includes a holding unit, the holding unit is configured to hold the first detection result of the light detection unit, and the stress detection unit is further configured to:
compare a second detection result of the light detection unit with the first detection result held by the holding unit; and
detect a change in the stress based on the comparison of the second detection result with the held first detection result.

8 . The substrate according to claim 1 , further comprising a plurality of light detection units between the base material unit and the first land, wherein
the plurality of light detection units includes the light detection unit, the stress detection unit is further configured to detect the stress based on a plurality of detection results of the plurality of the light detection units, and the plurality of detection results includes the first detection result.

9 . The substrate according to claim 1 , wherein the first land is in a recess in the base material unit.

10 . A semiconductor package, comprising:
a substrate; a semiconductor mountable on the substrate, wherein the semiconductor includes a plurality of terminals, a resin body, and a transparent body on the resin body; a first stress light emitting body configured to emit light based on a damage of a terminal of the plurality of terminals of the semiconductor; and a second stress light emitting body in contact with an outside of each of the resin body and the transparent body, wherein
the second stress light emitting body is configured to emit light based on a damage of a package of the semiconductor, and
the light emitted by the second stress light emitting body is detectable from outside of the semiconductor package.

11 . The semiconductor package according to claim 10 , wherein
the second stress light emitting body is a sheet-shaped stress light emitting body on an interface the resin body and a glass body of the package, and the glass body is the transparent body.

12 . The semiconductor package according to claim 10 , wherein
a light beam of the emitted light by the second stress light emitting body includes a wavelength different from a wavelength in a visible light band, and the wavelength of the light beam is a wavelength one of an ultraviolet ray or a near infrared ray.

13 . The semiconductor package according to claim 10 , wherein
the terminal is at a corner portion of the semiconductor among the plurality of terminals of the semiconductor, and the first stress light emitting body is only at the terminal that is at the corner portion of the semiconductor among the plurality of terminals of the semiconductor.

14 . The semiconductor package according to claim 10 , further comprising an image capturing device within a vicinity of the package of the semiconductor, wherein the image capturing device is configured to detect the light emitted by the second stress light emitting body.

15 . The semiconductor package according to claim 10 , wherein the second stress light emitting body includes at least one of:
strontium aluminate (SrAl 2 O 4 :Eu) doped with europium and structurally controlled, zinc sulfide (ZnS:Mn) or barium calcium titanate ((Ba, Ca) TiO 3 :Pr) doped with a transition metal or a rare earth, or calcium yttrium aluminate (CaYAl 3 O 7 :Ce).

Assignees

• Sony Group Corp
• Sony Semiconductor Solutions Corp

Inventors

• Miyazaki Hirohito
• Nishida Yuji
• Wright Christopher
• Elliott-Bowman Bernadette
• Beard Timothy

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W76/153

  having interconnections in passages through the insulating or insulated base · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title