Integrated circuit package with electro-optical interconnect circuitry

Patent metadata

Field	Value
Publication number	US-11327259-B2
Application number	US-201715835177-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Dec 7, 2017
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

First claim

What is claimed is:

1. An integrated circuit package, comprising:
processing circuitry formed on a first die disposed on a substrate of the integrated circuit package;
a transceiver formed on the first die or a second die disposed on the substrate of the integrated circuit package; and
an optical engine formed on a third die disposed on the substrate of the integrated circuit package, wherein the optical engine is coupled to the processing circuitry via the transceiver, and wherein the transceiver directly drives a channel driver of the optical engine via an interconnect bridge in the substrate.

2. The integrated circuit package of claim 1 , wherein the optical engine is coupled to an external optical cable configured to mate directly with the integrated circuit package.

3. The integrated circuit package of claim 1 , wherein the transceiver is formed on the second die disposed on the substrate of the integrated circuit package.

4. The integrated circuit package of claim 1 , wherein the transceiver comprises a transceiver physical-layer circuit, that directly drives the channel driver.

5. The integrated circuit package of claim 4 , wherein the transceiver physical-layer circuit comprises:
a serializer that directly drives the channel driver of the optical engine; and
a deserializer that directly receives signals from a transimpedance amplifier and limiting amplifier block in the optical engine.

6. The integrated circuit package of claim 1 , further comprising an additional optical engine mounted on top of the transceiver.

7. The integrated circuit package of claim 1 , wherein the interconnect bridge is embedded in the substrate to connect the transceiver and the channel driver of the optical engine.

8. The integrated circuit package of claim 1 , wherein the transceiver directly drives the channel driver of the optical engine using one or more analog signals transmitted via the interconnect bridge.

9. A method of operating a multichip package, wherein the multichip package comprises a main chip, an optical engine chip, and a transceiver chip, the method comprising:
with the main chip, sending digital signals to the transceiver chip;
with the transceiver chip, receiving the digital signals from the main chip and sending analog signals based on the digital signals to the optical engine chip; and
with the optical engine chip, receiving the analog signals from the transceiver chip and outputting corresponding optical signals to an external optical cable that is directly mated to the multichip package.

10. The method of claim 9 , further comprising:
with a physical-layer component in the transceiver chip, directly driving the optical engine chip.

11. The method of claim 10 , wherein directly driving the optical engine chip with the physical-layer component in the transceiver chip comprises:
with a serializer in the physical-layer component of the transceiver chip, directly driving a channel driver in the optical engine chip.

12. The method of claim 9 , comprising:
with a deserializer in the physical-layer component of the transceiver chip, directly receiving signals from a transimpedance and limiting amplifier block in the optical engine chip.

13. The method of claim 9 , wherein the transceiver chip sends the analog signals to the optical engine chip via an interconnect bridge embedded in a substrate on which the transceiver chip and the optical engine chip are disposed.

14. An integrated circuit system, comprising:
a package substrate;
an integrated circuit formed on the package substrate;
a transceiver formed on the package substrate; and
an optical engine formed on the package substrate, wherein the transceiver is configured to directly drive the optical engine using one or more analog signals transmitted from the transceiver to the optical engine via conductors embedded in the package substrate, and wherein the optical engine is configured to interface directly with an optical cable.

15. The integrated circuit system of claim 14 , wherein the transceiver comprises:
a media access controller;
a physical coding sublayer and forward error correction block configured to receive signals from the media access controller;
a serializer configured to receive signals from the physical coding sublayer and forward error correction block; and
a deserializer configured to output signals to the physical coding sublayer and forward error correction block.

16. The integrated circuit system of claim 15 , wherein the optical engine comprises:
a channel driver configured to be directly driven by the serializer;
an optical transmitter configured to receive signals from the channel driver;
an optical receiver; and
an amplifier block configured to receive signals from the optical receiver, wherein the amplifier block is configured to directly drive the deserializer.

17. The integrated circuit system of claim 14 , further comprising:
a first embedded multi-die interconnect bridge coupled between the integrated circuit and the transceiver; and
a second embedded multi-die interconnect bridge coupled between the transceiver and the optical engine, wherein the second embedded multi-die interconnect bridge comprises the conductors.

18. The integrated circuit system of claim 17 , wherein the integrated circuit is configured to conduct signals to the package substrate via solder bumps, wherein the integrated circuit is configured to conduct signals to the first embedded multi-die interconnect bridge only via microbumps, and wherein the microbumps are at least two times smaller than the solder bumps.

19. The system of claim 14 , wherein the conductors embedded in the package substrate comprise an embedded multi-die interconnect bridge.

20. The system of claim 14 , wherein the integrated circuit is configured to send one or more digital signals to the transceiver, wherein the transceiver is configured to generate the one or more analog signals based on the one or more digital signals.

Assignees

• Intel Corp

Inventors

• Li Peng
• Martinez Joel
• Long Jon

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/227

  Multiple bumps having different sizes · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title