Schmitt trigger with pull-up transistor

Patent metadata

Field	Value
Publication number	US-12494773-B2
Application number	US-202418443112-A
Country	US
Kind code	B2
Filing date	Feb 15, 2024
Priority date	Sep 20, 2021
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

First claim

The invention claimed is:

1 . A method, comprising:
receiving, at a main input of Schmitt trigger, an input voltage; receiving, with a reference voltage generator, a supply voltage; generating, with the reference voltage generator, a high reference voltage based on the supply voltage and lower than the supply voltage; generating, with a control signal generator coupled between the main input and a first inverter of the Schmitt trigger, a control signal having a value based on the input voltage; and providing the control signal to a control terminal of a pull-up transistor of the Schmitt trigger, wherein the pullup transistor is coupled between the first inverter of the Schmitt trigger and a second inverter of the Schmitt trigger and has a source terminal coupled to the high reference voltage, wherein the first and second inverters are coupled between the supply voltage and ground, wherein the control signal is equal to the high reference voltage when the input voltage is high, wherein the control signal is ground when the input voltage is low.

2 . The method of claim 1 , wherein a pass transistor is coupled between the first inverter and a second inverter of the Schmitt trigger.

3 . The method of claim 2 , wherein a drain terminal of the pull-up transistor is coupled between the pass transistor and the second inverter.

4 . The method of claim 1 , wherein a gate terminal of the pull-up transistor receives the control signal.

5 . The method of claim 4 , wherein the control signal is equal to the high reference voltage when the input voltage is high, wherein the control signal is 0 V when the input voltage is low.

6 . The method of claim 5 , comprising providing the high reference voltage from the pull-up transistor to an input of the second inverter when the input voltage is low.

7 . The method of claim 6 , wherein a source terminal of the pull-up transistor is coupled to the high reference voltage.

8 . The method of claim 2 , further comprising providing, with a supply voltage selector, either a low supply voltage or a high supply voltage as the supply voltage based on a mode selection value.

9 . The method of claim 8 , comprising generating, with the reference voltage generator, the high reference voltage based on the supply voltage and the mode selection value.

10 . A method, comprising:
receiving, with a supply voltage selector of an integrated circuit, a selection signal; outputting, with the supply voltage selector, and either a high supply voltage or a low supply voltage as a supply voltage responsive to the selection signal; generating, with a reference voltage generator, a reference voltage based on the supply voltage and lower than the supply voltage; and receiving, with a Schmitt trigger of the integrated circuit, the reference voltage and an input voltage; and generating, with a control signal generator of the Schmitt trigger, a control signal based on the input voltage; and providing the control signal to a gate terminal of a pull-up transistor having a source terminal receiving the reference voltage and a drain terminal coupled to an output of a first inverter of the Schmitt trigger and an input of a second inverter of the Schmitt trigger, wherein the first and second inverters are coupled between the supply voltage and ground.

11 . The method of claim 10 , comprising providing the reference voltage from the pull-up transistor to the input of the second inverter.

12 . The method of claim 10 , wherein the control signal is equal to the high reference voltage when the input voltage is high, wherein the control signal is 0 V when the input voltage is low.

13 . The method of claim 12 , comprising providing the high reference voltage from the pull-up transistor to an input of the second inverter when the input voltage is low.

14 . A method, comprising:
receiving, with a reference voltage generator, a supply voltage; generating, with the reference voltage generator, a high reference voltage lower than the supply voltage; receiving an input value at a main input of Schmitt trigger that includes a first inverter coupled to the main input, a second inverter coupled to the first inverter, and a main output coupled to the second inverter, the first and second inverters each being coupled between a supply voltage and ground; generating a feed-forward control signal based on the input value, wherein the feed-forward control signal is equal to the high reference voltage when the input voltage is high, wherein the control signal is 0 V when the input voltage is low; and providing the feed-forward control signal to a gate terminal of PMOS pull-up transistor having a drain terminal coupled to an input of the second inverter and a source terminal coupled to the high reference voltage.

15 . The method of claim 14 , comprising:
supplying the high reference voltage to a source terminal of the pull-up transistor.

16 . The method of claim 15 , wherein a pass transistor is coupled between an output of the first inverter and the input of the second inverter.

Assignees

• St Microelectronics Int Nv

Inventors

• Tiwari Manoj Kumar
• Rizvi Saiyid Mohammad Irshad

Classifications

• H03K3/3565 Primary

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K3/13

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• H03K3/0377 Primary

  Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165) · CPC title