Operational amplifier with current-controlled up or down hysteresis

Patent metadata

Field	Value
Publication number	US-9654086-B1
Application number	US-201614992426-A
Country	US
Kind code	B1
Filing date	Jan 11, 2016
Priority date	Jan 11, 2016
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

Disclosed is an op-amp circuit with current-controlled hysteresis that is insensitive to PVT variations. In the circuit, a digital output signal is output from an output buffer based on the output voltage at an output node of an op-amp. A current source is connected to the input side of the op-amp or one of multiple current sources is selectively connected to the input side and enabled when the digital output signal has a high value to provide falling edge hysteresis. Alternatively, a current source is connected to the reference side of the op-amp or one of multiple current sources is selectively connected to the reference side and enabled when the digital output signal is low to provide rising edge hysteresis. Alternatively, current sources are connected to both the input and reference sides and selectively controlled to provide either falling or rising edge hysteresis.

First claim

What is claimed is:

1. A circuit structure comprising:
an operational amplifier comprising:
a pair of stacked first transistors;
an output node;
a pair of stacked second transistors connected in series to the output node;
at least one third transistor, the pair of stacked first transistors and the pair of stacked second transistors being connected to the third transistor; and,
a trip point adjustment node between the stacked first transistors;
a current source electrically connected to the trip point adjustment node; and
an output buffer electrically connected between the output node and the current source, the output buffer outputting a digital output signal based on an output voltage at the output node and the current source being selectively disabled when the digital output signal has a first value and selectively enabled to adjust a voltage level at the trip point adjustment node by a predetermined amount when the digital output signal has a second value to provide falling edge hysteresis.

2. The circuit structure of claim 1 ,
the current source comprising at least two stacked additional transistors electrically connected in series between the trip point adjustment node and ground,
the stacked first transistors, the stacked second transistors, the third transistor and the stacked additional transistors comprising N-type field effect transistors, and
the output buffer applying the digital output signal to a gate of a most distal of the stacked additional transistors from the trip point adjustment node.

3. The circuit structure of claim 2 ,
the output voltage varying depending upon a difference between an input voltage applied to first gates of the stacked first transistors and a reference voltage applied to second gates of the stacked second transistors,
when the input voltage is above the reference voltage, the output voltage is relatively high such that the digital output signal has a high value and the current source is enabled, pulling down the voltage level on the trip point adjustment node by the predetermined amount to provide falling edge hysteresis, ensuring that the digital output signal will only be switched to a low value when the input voltage has dropped below the reference voltage by the predetermined amount, and
when the input voltage has dropped below the reference voltage by the predetermined amount, the output voltage is relatively low such that digital output signal switches to the low value and the current source is disabled, allowing the digital output signal to be switch back to the high value only when the input voltage has risen above the reference voltage.

4. The circuit structure of claim 3 , the reference voltage being a bandgap reference voltage from a bandgap reference voltage circuit and a gate of the third transistor being controlled by a common mode voltage from the bandgap reference voltage circuit.

5. The circuit structure of claim 2 , the predetermined amount being dependent upon sizes of the stacked additional transistors.

6. The circuit structure of claim 1 , further comprising a multiplexer connected to the trip point adjustment node and a set of different current sources, the set of different current sources includes the current source, the multiplexer receiving a select signal and, based on the select signal, selectively connecting one specific current source of the set of different current sources to the trip point adjustment node so as to allow the voltage level at the trip point adjustment node to be adjusted by a selected predetermined amount.

7. The circuit structure of claim 1 , the operational amplifier further comprising a current mirror, the pair of stacked first transistors and the pair of stacked second transistors being electrically connected to different sides of the current mirror.

8. A circuit structure comprising:
an operational amplifier comprising:
a pair of stacked first transistors;
an output node;
a pair of stacked second transistors connected in series to the output node;
at least one third transistor, the pair of stacked first transistors and the pair of stacked second transistors being connected to the third transistor; and,
a trip point adjustment node between the stacked second transistors;
a current source electrically connected to the trip point adjustment node; and
the output buffer outputting a digital output signal based on an output voltage at the output node and the current source being selectively enabled to adjust a voltage level at the trip point adjustment node by a predetermined amount when the digital output signal has a first value and being selectively disabled when the digital output signal has a second value.

9. The circuit structure of claim 8 ,
the current source comprising at least two stacked additional transistors electrically connected in series between the trip point adjustment node and ground,
the stacked first transistors, the stacked second transistors, the third transistor and the stacked additional transistors comprising N-type field effect transistors, and
the circuit structure further comprising an inverter receiving the digital output signal from the output buffer, converting the digital output signal into an inverted digital output signal and applying the inverted digital output signal to a gate of a most distal of the stacked additional transistors from the trip point adjustment node.

10. The circuit structure of claim 9 ,
the output voltage varying depending upon a difference between an input voltage applied to first gates of the stacked first transistors and a reference voltage applied to second gates of the stacked second transistors,
when the input voltage is below the reference voltage, the output voltage is relatively low such that the digital output signal has a low value, the inverted digital output signal has a high value and the current source is enabled, pulling down the voltage level on the trip point adjustment node by the predetermined amount to provide rising edge hysteresis, ensuring that the digital output signal will only be switched to the high value when the input voltage has risen above the reference voltage by the predetermined amount, and
when the input voltage has risen above the reference voltage by the predetermined amount, the output voltage is relatively high such that digital output signal switches to the high value, the inverted digital output signal switches to the low value and the current source is disabled, allowing the digital output signal to be switch back to the low value only when the input voltage has fallen below the reference voltage.

11. The circuit structure of claim 10 , the reference voltage being a bandgap reference voltage from a bandgap reference voltage circuit and a gate of the third transistor being controlled by a common mode voltage from the bandgap reference voltage circuit.

12. The circuit structure of claim 9 , the predetermined amount being dependent upon sizes of the stacked additional transistors.

13. The circuit structure of claim 8 , further comprising a multiplexer connected to the trip point adjustment node and a set of different current sources, the set of different current sources includes the current source, the multiplexer receiving a select signal and, based on the select signal, selectively connecting one specific current source of the set of different current sources to the trip point adjustment node so as to allow the voltage level at the trip point adjustment node to be adjusted by a selected predetermined amount.

14. The circuit structure of claim 8 , the operational amplifier further comprising a current mirror, the pair of stacked

Assignees

• Globalfoundries Inc

Inventors

• Fifield John A
• Hunt-Schroeder Eric D

Classifications

• H03K3/02337 Primary

  Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165) · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03K3/011

  Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title