CMOS Schmitt trigger circuit and associated methods

Patent metadata

Field	Value
Publication number	US-9467125-B2
Application number	US-201414573129-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 17, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

The Schmitt trigger circuit includes a signal input, a first inverter coupled to the signal input and configured to operate at a first voltage, and a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage. A protection device is coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage. A feedback circuit is coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis. An output circuit is coupled to the second inverter and configured to provide an output signal at the second voltage. The approach provides an architecture for 3.3V receivers designed by using 1.8V devices, without active power consumption from the I/O PAD during transition, and/or that supports CMOS standard levels for 1.8V and 3.3V receivers.

First claim

That which is claimed is:

1. A Schmitt trigger circuit comprising:
a signal input;
a first inverter coupled to the signal input and configured to operate at a first voltage;
a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage;
a protection device coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage;
a feedback circuit coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis; and
an output circuit coupled to the second inverter and configured to provide an output signal at the second voltage.

2. The Schmitt trigger circuit according to claim 1 wherein the first inverter comprises a plurality of transistor devices configured to operate at the second voltage and coupled together.

3. The Schmitt trigger circuit according to claim 2 wherein the plurality of transistor devices of the first inverter comprises a series of cascode coupled transistor devices to protect the devices from over-voltage stress.

4. The Schmitt trigger circuit according to claim 3 wherein the series of cascade coupled transistor devices of the first inverter is coupled between a first supply voltage and ground.

5. The Schmitt trigger circuit according to claim 1 wherein the protection device comprises a transistor clipping circuit controlled by a first reference voltage which corresponds to the second voltage.

6. The Schmitt trigger circuit according to claim 1 wherein the first inverter, the second inverter, the protection device, the feedback circuit and the output circuit each comprises 1.8V transistor devices, and the first voltage level is 3.3V.

7. The Schmitt trigger circuit according to claim 1 wherein the feedback circuit comprises a positive feedback latch.

8. A CMOS input/output (I/O) receiver comprising:
an I/O pad;
a Schmitt trigger circuit coupled to the I/O pad;
a down level shifter device coupled to the Schmitt trigger circuit; and
an internal reference voltage generator configured to generate reference voltages for the Schmitt trigger circuit and the down level shifter device based upon a supply voltage;
the Schmitt trigger circuit comprising
a first inverter coupled to the I/O pad and configured to operate at a first voltage,
a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage,
a protection device coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage,
a feedback circuit coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis, and
an output circuit coupled to the second inverter and configured to provide an output signal at the second voltage to the down level shifter device.

9. The CMOS input/output (I/O) receiver according to claim 8 wherein the first inverter comprises a plurality of transistor devices configured to operate at the second voltage level and coupled together.

10. The CMOS input/output (I/O) receiver circuit according to claim 9 wherein the plurality of transistor devices of the first inverter comprises a series of cascode coupled transistor devices to protect the devices from over-voltage stress.

11. The CMOS input/output (I/O) receiver according to claim 10 wherein the series of cascode coupled transistor devices of the first inverter is coupled between the first supply voltage and ground.

12. The CMOS input/output (I/O) receiver according to claim 8 wherein the protection device comprises a transistor clipping circuit controlled by a first reference voltage from the internal reference voltage generator which corresponds to the second voltage.

13. The CMOS input/output (I/O) receiver according to claim 8 wherein the first inverter, the second inverter, the protection device, the feedback circuit and the output circuit each comprise 1.8V transistor devices, and the first voltage level is 3.3V.

14. The CMOS input/output (I/O) receiver according to claim 8 wherein the feedback circuit comprises a positive feedback latch.

15. A method of implementing a Schmitt trigger circuit, the method comprising:
coupling a first inverter, configured to operate at a first voltage, to a signal input;
coupling a second inverter downstream of the first inverter and configured to operate at a second voltage lower than the first voltage;
coupling a protection device between the first inverter and the second inverter to limit voltage input to the second inverter at the second voltage;
coupling a feedback circuit downstream of the protection device between the first inverter and the second inverter to introduce hysteresis; and
coupling an output circuit to the second inverter to provide an output signal at the second voltage.

16. The method according to claim 15 wherein coupling the first inverter comprises providing a plurality of transistor devices configured to operate at the second voltage level and coupled together.

17. The method according to claim 16 wherein providing the plurality of transistor devices of the first inverter comprises coupling a series of transistor devices in a cascade arrangement to protect the devices from over-voltage stress.

18. The method according to claim 17 wherein the series of cascode coupled transistor devices of the first inverter is coupled between a first supply voltage and ground.

19. The method according to claim 15 wherein coupling the protection device comprises providing a transistor clipping circuit controlled by a first reference voltage which corresponds to the second voltage.

20. The method according to claim 15 wherein the first inverter, the second inverter, the protection device, the feedback circuit and the output circuit each comprise 1.8V transistor devices, and the first voltage level is 3.3V.

21. The method according to claim 15 wherein coupling the feedback circuit comprises providing a positive feedback latch.

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Vinod
• Rizvi Saiyid Mohammad Irshad

Classifications

• H03K3/3565 Primary

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title