Aging-resistant schmitt receiver circuit

Patent metadata

Field	Value
Publication number	US-2022123738-A1
Application number	US-202117502548-A
Country	US
Kind code	A1
Filing date	Oct 15, 2021
Priority date	Oct 16, 2020
Publication date	Apr 21, 2022
Grant date	—

Abstract

A receiver circuit may include a first stage and a second stage. The first stage may include a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal. The second stage may determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit.

First claim

What is claimed is:

1 . A circuit, comprising:
a first stage comprising a first inverter circuit to generate a first signal based on an input signal and a second inverter circuit to generate a second signal based on the input signal, wherein the first stage is powered by a first power-supply-voltage range; and a second stage to determine a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit, wherein the second stage is powered by a second power-supply-voltage range that is greater than the first power-supply-voltage range.

2 . The circuit of claim 1 , comprising a first clamp circuit and a second clamp circuit,
wherein each of the first clamp circuit and the second clamp circuit outputs the input signal when the input signal is within a respective voltage range and outputs a constant voltage when the input signal is beyond the respective voltage range, wherein an output of the first clamp circuit is provided as an input to the first inverter circuit, and wherein an output of the second clamp circuit is provided as an input to the second inverter circuit.

3 . The circuit of claim 1 , comprising a latch circuit to store the logic state of the input signal determined by the second stage.

4 . The circuit of claim 1 , wherein the first stage separately implements a high-trip voltage and a low-trip voltage that are used to determine the logic state of the input signal.

5 . The circuit of claim 1 , wherein the second stage comprises a comparator circuit.

6 . The circuit of claim 5 , wherein the comparator circuit comprises a set of p-type metal-oxide-semiconductor (PMOS) transistors and a set of n-type metal-oxide-semiconductor (NMOS) transistors coupled in series.

7 . The circuit of claim 6 , wherein the first signal is provided to a gate of a PMOS transistor in the set of PMOS transistors and the second signal is provided to a gate of an NMOS transistor in the set of NMOS transistors.

8 . A method, comprising:
generating, by a first inverter circuit, a first signal based on an input signal, wherein the first inverter circuit is powered by a first power-supply-voltage range; generating, by a second inverter circuit, a second signal based on the input signal, wherein the second inverter circuit is powered by the first power-supply-voltage range; and determining, by a third circuit, a logic state of the input signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit, wherein the third circuit is powered by a second power-supply-voltage range that is greater than the first power-supply-voltage range.

9 . The method of claim 8 , comprising:
outputting, by a first clamp circuit, the input signal when the input signal is within a first voltage range, and a first constant voltage when the input signal is outside the first voltage range; outputting, by a second clamp circuit, the input signal when the input signal is within a second voltage range, and a second constant voltage when the input signal is outside the second voltage range; providing an output of the first clamp circuit to the first inverter circuit; and providing an output of the second clamp circuit to the second inverter circuit.

10 . The method of claim 8 , comprising storing, by a latch circuit, the logic state of the input signal determined by the third circuit.

11 . The method of claim 8 , wherein a high-trip voltage and a low-trip voltage that are used to determine the logic state of the input signal are determined by the first inverter circuit and the second inverter circuit, respectively.

12 . The method of claim 8 , wherein the third circuit is a comparator circuit.

13 . The method of claim 12 , wherein the comparator circuit comprises a set of p-type metal-oxide-semiconductor (PMOS) transistors and a set of n-type metal-oxide-semiconductor (NMOS) transistors coupled in series.

14 . The method of claim 13 , wherein the first signal is provided to a gate of a PMOS transistor in the set of PMOS transistors and the second signal is provided to a gate of an NMOS transistor in the set of NMOS transistors.

15 . A receiver circuit, comprising:
an input pad to receive a digital signal; a first stage comprising a first inverter circuit to generate a first signal based on the digital signal and a second inverter circuit to generate a second signal based on the digital signal; a second stage to determine a logic state of the digital signal by combining the first signal generated by the first inverter circuit and the second signal generated by the second inverter circuit; and a latch circuit to store the logic state of the digital signal determined by the second stage.

16 . The receiver circuit of claim 15 , comprising a first clamp circuit and a second clamp circuit, wherein each clamp circuit restricts a voltage range of the input signal, and wherein an output of each clamp circuit is provided as an input to a corresponding inverter circuit.

17 . The receiver circuit of claim 15 , wherein the first stage independently controls a high-trip voltage and a low-trip voltage that are used to determine the logic state of the input signal.

18 . The receiver circuit of claim 15 , wherein the second stage comprises a comparator circuit.

19 . The receiver circuit of claim 18 , wherein the comparator circuit comprises a set of p-type metal-oxide-semiconductor (PMOS) transistors and a set of n-type metal-oxide-semiconductor (NMOS) transistors coupled in series.

20 . The receiver circuit of claim 19 , wherein the first signal is provided to a gate of a PMOS transistor in the set of PMOS transistors and the second signal is provided to a gate of an NMOS transistor in the set of NMOS transistors.

Assignees

• Synopsys Inc

Inventors

• Gupta Rahul
• Bansal Nitin
• Thotli Akhil
• Puli Manoj Kumar Reddy

Classifications

• H03K3/3565

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• H03K3/0377 Primary

  Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165) · CPC title