Three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12490430-B2
Application number	US-202217570123-A
Country	US
Kind code	B2
Filing date	Jan 6, 2022
Priority date	Aug 23, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
a stack structure comprising interleaved conductive layers and first dielectric layers; a channel structure extending through the stack structure along a first direction in contact with a source of the 3D memory device at a bottom portion of the channel structure, the channel structure comprising a dielectric core, a semiconductor channel over the dielectric core, and a memory film over the semiconductor channel; and a conductive layer disposed under the stack structure, wherein the dielectric core is surrounded by the semiconductor channel at the bottom portion of the channel structure, and a first diameter of the dielectric core at the bottom portion of the channel structure is smaller than a second diameter of the dielectric core at an upper portion of the channel structure; wherein the memory film comprises a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer; wherein the tunneling layer, the storage layer, and the blocking layer are in direct contact with the conductive layer; and wherein a first thickness of the memory film at the bottom portion of the channel structure is greater than a second thickness of the memory film at the upper portion of the channel structure.

2 . The 3D memory device of claim 1 , wherein the semiconductor channel comprises a first angled structure, and a third diameter of the semiconductor channel at the bottom portion of the channel structure below the first angled structure is smaller than a fourth diameter of the semiconductor channel at the upper portion of the channel structure above the first angled structure.

3 . The 3D memory device of claim 1 , wherein the dielectric core at the upper portion of the channel structure comprises a hollow structure.

4 . The 3D memory device of claim 1 , wherein the dielectric core at the bottom portion of the channel structure comprises a solid pillar structure.

5 . The 3D memory device of claim 1 ,
wherein the conductive layer is in direct contact with the semiconductor channel.

6 . The 3D memory device of claim 5 , wherein the conductive layer comprises a polysilicon layer.

7 . The 3D memory device of claim 5 , wherein the conductive layer is in direct contact with the memory film.

8 . The 3D memory device of claim 5 , wherein the conductive layer surrounds the bottom portion of the channel structure.

9 . The 3D memory device of claim 8 , wherein the conductive layer is in direct contact with a bottom surface of the semiconductor channel and a portion of a side surface of the semiconductor channel at the bottom portion of the channel structure.

10 . The 3D memory device of claim 5 , further comprising:
a contact pad disposed under the conductive layer.

11 . The 3D memory device of claim 10 , wherein the contact pad is in direct contact with the conductive layer.

12 . The 3D memory device of claim 1 ,
wherein a thickness of the blocking layer at the bottom portion of the channel structure is greater than the thickness of the blocking layer at the upper portion of the channel structure.

13 . The 3D memory device of claim 12 , wherein a thickness of the tunneling layer at the bottom portion of the channel structure is equal to the thickness of the tunneling layer at the upper portion of the channel structure.

14 . The 3D memory device of claim 12 , wherein a thickness of the storage layer at the bottom portion of the channel structure is equal to the thickness of the storage layer at the upper portion of the channel structure.

15 . The 3D memory device of claim 12 , wherein the blocking layer comprises a silicon oxide layer.

16 . The 3D memory device of claim 12 , wherein the storage layer comprises a silicon nitride layer.

17 . The 3D memory device of claim 12 , wherein the tunneling layer comprises a silicon oxide layer.

18 . The 3D memory device of claim 1 , further comprising:
a dummy channel structure extending through the stack structure along the first direction in contact with the source of the 3D memory device.

19 . The 3D memory device of claim 18 , wherein further comprising: a contact structure extending along the first direction.

20 . The 3D memory device of claim 1 , wherein a bottom surface of the memory film is above a bottom surface of the semiconductor channel.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Linchun
• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang
• Xie Wei
• Wang Di
• Wang Bingguo
• Huo Zongliang

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title