Memory Arrays And Methods Used In Forming A Memory Array

Patent metadata

Field	Value
Publication number	US-2020168622-A1
Application number	US-201816200158-A
Country	US
Kind code	A1
Filing date	Nov 26, 2018
Priority date	Nov 26, 2018
Publication date	May 28, 2020
Grant date	—

Abstract

A method used in forming a memory array comprises forming a tier comprising conductor material above a substrate. Sacrificial islands comprising etch-stop material are formed directly above the conductor material of the tier comprising the conductor material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the sacrificial islands and the tier comprising the conductor material. Etching is conducted through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material. The sacrificial islands are removed through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material. Channel material is formed in the extended-channel openings to the tier comprising the conductor material. The channel material is electrically coupled with the conductor material of the tier comprising the conductor material. Structure independent of method is disclosed.

First claim

1 . A method used in forming a memory array, comprising:
forming a tier comprising conductor material above a substrate; forming sacrificial islands comprising etch-stop material directly above the conductor material of the tier comprising the conductor material; forming a stack comprising vertically-alternating insulative tiers and wordline tiers above the sacrificial islands and the tier comprising the conductor material; etching through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material; removing the sacrificial islands through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material; and forming channel material in the extended-channel openings to the tier comprising the conductor material, the channel material being electrically coupled with the conductor material of the tier comprising the conductor material.

2 . The method of claim 1 wherein the etch-stop material comprises conductive material.

3 . The method of claim 1 wherein the etch-stop material comprises a radially outer dielectric material and a radially inner conductive material.

4 . The method of claim 1 wherein the individual islands are diametrically larger than the individual channel openings prior to said removing.

5 . The method of claim 1 wherein the sacrificial islands and the etch-stop material are in a tier comprising insulator material of different composition from that of the etch-stop material.

6 . The method of claim 5 wherein the individual islands are diametrically larger than the individual channel openings prior to said removing, said removing forming an annular recess in the tier comprising the insulator material and that projects radially-outward, and further comprising forming charge-blocking material in the annular recess prior to forming the channel material.

7 . The method of claim 6 comprising forming charge-storage material in the annular recess prior to forming the channel material.

8 . The method of claim 7 comprising forming insulative charge-passage material in the annular recess prior to forming the channel material.

9 . The method of claim 6 wherein none of the channel material is formed in the annular recess.

10 . The method of claim 1 comprising:
forming a tier comprising insulator material before forming the sacrificial islands, the insulator material being of different composition from that of the etch-stop material;
forming a conductor tier above the tier comprising the insulator material before forming the stack; and
forming the sacrificial islands in the conductor and in the tier comprising the insulator material.

11 . The method of claim 10 wherein the individual islands are diametrically larger than the individual channel openings prior to said removing, said removing forming an annular recess in the tier comprising the insulator material and in the conductor tier, the annular recess projecting radially-outward, and further comprising forming charge-blocking material in the annular recess prior to forming the channel material.

12 . The method of claim 10 comprising:
forming multiple of said conductor tier above the tier comprising the insulator material; and
forming the sacrificial islands in said multiple of said conductor tiers above the tier comprising the insulator material.

13 . The method of claim 12 wherein the individual islands are diametrically larger than the individual channel openings prior to said removing, said removing forming an annular recess in the tier comprising the insulator material and said multiple of said conductor tiers above the tier comprising the insulator material, the annular recess projecting radially-outward, and further comprising forming charge-blocking material in the annular recess prior to forming the channel material.

14 . A method used in forming a memory array, comprising:
forming a tier comprising conductor material above a substrate; forming sacrificial islands spaced from and between lines, the sacrificial islands and the sacrificial lines being directly above the conductor material of the tier comprising the conductor material, the sacrificial islands and the lines comprising etch-stop material; forming a stack comprising vertically-alternating insulative tiers and wordline tiers above the sacrificial islands, the lines, and the tier comprising the conductor material; etching through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material; removing the sacrificial islands through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material; forming channel material in the extended-channel openings to the tier comprising the conductor material, the channel material being electrically coupled with the conductor material of the tier comprising the conductor material; and etching through the insulative tiers and the wordline tiers to the etch-stop material of the lines to form horizontally-elongated trenches that have individual bases comprising the etch-stop material of individual of the lines.

15 . The method of claim 14 wherein the sacrificial islands and the lines comprise conductive etch-stop material and the lines are sacrificial, and further comprising removing the conductive sacrificial lines through individual of the horizontally-elongated trenches.

16 . The method of claim 14 wherein the sacrificial islands and the lines comprise insulative etch-stop material and the lines are sacrificial, and further comprising removing the insulative sacrificial lines through individual of the horizontally-elongated trenches.

17 . The method of claim 14 wherein the sacrificial islands and the lines comprise insulative etch-stop material.

18 . The method of claim 14 wherein the etching through the insulative tiers and the wordline tiers to the etch-stop material of the sacrificial lines occurs after the forming of the channel material.

19 . A method used in forming a memory array, comprising:
forming a tier comprising conductor material above a substrate; forming sacrificial islands spaced from and between non-sacrificial lines, the sacrificial islands and the non-sacrificial lines being directly above the conductor material of the tier comprising the conductor material, the sacrificial islands and the non-sacrificial lines comprising insulative etch-stop material; forming a stack comprising vertically-alternating insulative tiers and wordline tiers above the sacrificial islands, the non-sacrificial lines, and the tier comprising the conductor material; etching through the insulative tiers and the wordline tiers to the insulative etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the insulative etch-stop material; removing the sacrificial islands through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material; forming channel material in the extended-channel openings to the tier comprising the conductor material, the channel material being electrically coupled with the conductor material of the tier comprising the conductor material; etching through the insulative tiers and the wordline tiers

Assignees

• Micron Technology Inc

Inventors

• Fukuzumi Yoshiaki
• Barclay M Jared
• Camerlenghi Emilio
• Tessariol Paolo

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic

• H01L21/76802

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L21/76831

  Electricity · mapped topic