Semiconductor device including vertical memory structure and separation structure each including side surface slope changing portion and data storage system including the same

Patent metadata

Field	Value
Publication number	US-12490428-B2
Application number	US-202217656088-A
Country	US
Kind code	B2
Filing date	Mar 23, 2022
Priority date	Mar 24, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A semiconductor device includes a stack structure and an insulation structure that covers the stack structure, a vertical memory structure that penetrates the stack structure, and a separation structure that penetrates the stack structure and has an upper surface located at a higher level than an upper surface of the vertical memory structure. The stack structure includes three gate stack groups stacked in a vertical direction. Each of the three gate stack groups includes gate layers stacked and spaced apart from each other in the vertical direction. At a height level between a lowermost gate layer and an uppermost gate layer, a side surface of the vertical memory structure includes memory side surface slope changing portions, and a side surface of the separation structure includes separation side surface slope changing portions positioned at substantially a same height level as some of the memory side surface slope changing portions.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first structure; a second structure that includes a stack structure and an insulation structure that covers at least a portion of the stack structure; a vertical memory structure that penetrates through at least the stack structure; and a separation structure that penetrates through at least the stack structure and that has an upper surface located at a higher level than an upper surface of the vertical memory structure, wherein the stack structure includes at least three gate stack groups that are stacked on the first structure in a vertical direction, each of the at least three gate stack groups includes a plurality of gate layers that are stacked and spaced apart from each other in the vertical direction, at a height level between a lowermost gate layer and an uppermost gate layer of the plurality of gate layers of the stack structure, a side surface of the vertical memory structure includes a plurality of “N” memory side surface slope changing portions, a side surface of the separation structure includes “M” of separation side surface slope changing portion that is positioned at substantially a same height level as “M” of memory side surface slope changing portion of the plurality of “N” memory side surface slope changing portions, wherein “M”< “N”, “N” is a natural number of 2 or greater, “M” is a natural number of 1 or greater, and at a higher level than the uppermost gate layer, the side surface of the vertical memory structure includes a first upper slope changing portion.

2 . The semiconductor device of claim 1 , wherein
each of the plurality of “N” memory side surface slope changing portions and the “M” of separation side surface slope changing portion has a first slope between an upper side surface portion and a lower side surface portion, and the first slope is less steep than a slope of each of the upper side surface portion and the lower side surface portion.

3 . The semiconductor device of claim 1 , wherein
the at least three gate stack groups include a first gate stack group, a second gate stack group, and a third gate stack group that are sequentially stacked in the vertical direction, “N” is 2, and “M” is 1, and the separation side surface slope changing portion is located at a same height level as that of a higher memory side surface slope changing portion of two of the plurality of memory side surface slope changing portions.

4 . The semiconductor device of claim 1 , wherein
the at least three gate stack groups include a first gate stack group, a second gate stack group, a third gate stack group, and a fourth gate stack group that are sequentially stacked in the vertical direction, “N” is 3, and “M” is 2, and two of the separation side surface slope changing portions are located at substantially a same height level as two of the memory side surface slope changing portions that are positioned at a higher level than a lowermost memory side surface slope changing portion of three of the memory side surface slope changing portions.

5 . The semiconductor device of claim 1 , wherein
the at least three gate stack groups include a first gate stack group, a second gate stack group, a third gate stack group, and a fourth gate stack group that are sequentially stacked in the vertical direction, “N” is 3, and “M” is 1, and the separation side surface slope changing portion is located at substantially a same height level as an intermediate memory side surface slope changing portion positioned between a lowermost memory side surface slope changing portion and an uppermost memory side surface slope changing portion of three of the memory side surface slope changing portions.

6 . The semiconductor device of claim 1 , wherein,
on the side surface of the vertical memory structure, the plurality of “N” memory side surface slope changing portions are disposed between the at least three gate stack groups adjacent to each other in the vertical direction.

7 . The semiconductor device of claim 1 , wherein,
at a higher level than the uppermost gate layer, the side surface of the separation structure includes a second upper slope changing portion.

8 . The semiconductor device of claim 7 , wherein
the first upper slope changing portion and the second upper slope changing portion are located at substantially a same height level.

9 . The semiconductor device of claim 1 , further comprising:
a support vertical structure, wherein the gate layers are stacked and spaced apart from each other in a first region of the second structure in the vertical direction and extend from the first region of the second structure to a second region of the second structure, the gate layers include gate pads arranged in a step shape in the second region of the second structure, the vertical memory structure penetrates through the gate layers in the first region of the second structure, the support vertical structure penetrates through the gate layers in the second region of the second structure, and at the height level between the lowermost gate layer and the uppermost gate layer, a side surface of the support vertical structure includes a plurality of “N” support side surface slope changing portions each located at substantially a same height level as the plurality of “N” memory side surface slope changing portions.

10 . The semiconductor device of claim 1 , further comprising:
a peripheral contact plug that penetrates through a portion of at least the second structure, wherein the peripheral contact plug is spaced apart from the gate layers of the stack structure, and at the height level between the lowermost gate layer and the uppermost gate layer, a side surface of the peripheral contact plug includes a plurality of “N” peripheral contact side surface slope changing portions located at substantially a same height level as the plurality of “N” memory side surface slope changing portions.

11 . The semiconductor device of claim 10 , wherein,
at a higher level than the uppermost gate layer, a side surface of the peripheral contact plug includes an upper slope changing portion, an upper surface of the peripheral contact plug is located at a higher level than an upper surface of the vertical memory structure, and a lower surface of the peripheral contact plug is located at a lower level than a lower surface of the vertical memory structure.

12 . The semiconductor device of claim 1 , further comprising:
gate contact plugs, wherein the gate layers are stacked in a first region of the second structure in the vertical direction and extend from the first region of the second structure into a second region of the second structure, the gate layers include gate pads arranged in a step shape in the second region of the second structure, the gate contact plugs penetrate through the gate pads and electrically connect to the gate pads, each of the gate contact plugs includes a lower surface at a lower level than the lowermost gate layer and an upper surface at a higher level than the uppermost gate layer, and at the height level between the lowermost gate layer and the uppermost gate layer, a side surface of one of the gate contact plugs includes a plurality of “N” gate contact side surface slope changing portions located at substantially a same height level as the plurality of “N” memory side surface slope changing portions.

13 . The semiconductor device of claim 12 , wherein,
at a higher level than the uppermost gate layer, a side surface of one of the gate contact plugs includes at least two upper slope changing portions.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Giyong
• Kim Seungyoon
• Sim Jaeryong
• Han Jeehoon

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title