Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture
US-12490272-B2 · Dec 2, 2025 · US
This page is not indexed by search engines while we improve data quality.
Patent family 89432937
This patent family groups 2 related publications across US. Members often share priority claims or equivalent filings in different countries.
| Field | Value |
|---|---|
| Family ID | 89432937 |
| Family type | — |
| Earliest priority | Jun 29, 2022 |
| First filing country | US |
| Member publications | 2 |
| Countries | US |
| Representative publication | US12490272B2 — Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture |
Representative publication
Best representative member for this family based on priority and filing country.
US12490272B2 — Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture (published Dec 2, 2025)
Member publications
Related publications in this family.