Apparatuses, methods, and systems for a user defined formatting instruction to configure multicast benes network circuitry

Patent metadata

Field	Value
Publication number	US-2020409701-A1
Application number	US-201916457994-A
Country	US
Kind code	A1
Filing date	Jun 29, 2019
Priority date	Jun 29, 2019
Publication date	Dec 31, 2020
Grant date	—

Abstract

Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described. In one embodiment, a processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and an execution unit to execute the decoded single instruction to: send the packed control data to respective control inputs of a circuit that comprises an inverse butterfly circuit coupled in series to a butterfly circuit, wherein the inverse butterfly circuit comprises a first plurality of stages of multicast switches and the butterfly circuit comprises a second plurality of stages of multicast switches, read, once from storage separate from the circuit, each element of the packed input data as respective inputs of the circuit, route the packed input data through the circuit according to the packed control data, and store resultant packed data from the circuit into the packed data destination.

First claim

What is claimed is:

1 . A processor comprising:
a decoder to decode a single instruction into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and an execution unit to execute the decoded single instruction to:
send the packed control data to respective control inputs of a circuit that comprises an inverse butterfly circuit coupled in series to a butterfly circuit, wherein the inverse butterfly circuit comprises a first plurality of stages of multicast switches and the butterfly circuit comprises a second plurality of stages of multicast switches, each of the first plurality of stages of multicast switches of the inverse butterfly circuit and each of the second plurality of stages of multicast switches of the butterfly circuit comprise a same number of data inputs, and a number of controls bits for each stage is at least the number of data inputs for each stage,
read, once from storage separate from the circuit, each element of the packed input data as respective inputs of the circuit,
route the packed input data through the circuit according to the packed control data, and
store resultant packed data from the circuit into the packed data destination.

2 . The processor of claim 1 , wherein the execution unit executes the decoded single instruction to route the packed input data through the circuit according to the packed control data that generates a data path sequence of a set of sliding windows from the one read of the packed input data.

3 . The processor of claim 1 , wherein the execution unit executes the decoded single instruction to route the packed input data through the circuit according to the packed control data that generates a data path sequence of a set of sliding windows and a symmetric data path sequence of a set of reverse order sliding windows from the one read of the packed input data from the storage.

4 . The processor of claim 1 , wherein the execution unit executes the decoded single instruction to route the packed input data through the circuit according to the packed control data that generates a data path sequence or a coefficient sequence of a multiphase filter pattern from the one read of the packed input data from the storage.

5 . The processor of claim 1 , wherein the execution unit executes the decoded single instruction to route the packed input data through the circuit according to the packed control data to select every other element of the packed input data as the respective inputs of the circuit, and generate a data path sequence of a set of sliding windows from the every other element of the packed input data.

6 . The processor of claim 1 , wherein the execution unit executes the decoded single instruction to route the packed input data through the circuit according to the packed control data that generates a data path sequence of irregularly spaced samples from the one read of the packed input data from the storage.

7 . The processor of claim 1 , wherein the execution unit executes the decoded single instruction to route the packed input data through the circuit according to the packed control data in a first mode for real numbers and in a second, different mode for complex numbers.

8 . The processor of claim 1 , wherein the execution unit executes a plurality of instances of the single instruction in a same software loop, and the packed input data and the packed control data are passed to the plurality of instances of the single instruction through a pre-computed header.

9 . A method comprising:
decoding a single instruction with a decoder of a processor into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and executing the decoded single instruction with an execution unit of the processor to:
send the packed control data to respective control inputs of a circuit that comprises an inverse butterfly circuit coupled in series to a butterfly circuit, wherein the inverse butterfly circuit comprises a first plurality of stages of multicast switches and the butterfly circuit comprises a second plurality of stages of multicast switches, each of the first plurality of stages of multicast switches of the inverse butterfly circuit and each of the second plurality of stages of multicast switches of the butterfly circuit comprise a same number of data inputs, and a number of controls bits for each stage is at least the number of data inputs for each stage,
read, once from storage separate from the circuit, each element of the packed input data as respective inputs of the circuit,
route the packed input data through the circuit according to the packed control data, and
store resultant packed data from the circuit into the packed data destination.

10 . The method of claim 9 , wherein the executing the decoded single instruction routes the packed input data through the circuit according to the packed control data that generates a data path sequence of a set of sliding windows from the one read of the packed input data.

11 . The method of claim 9 , wherein the executing the decoded single instruction routes the packed input data through the circuit according to the packed control data that generates a data path sequence of a set of sliding windows and a symmetric data path sequence of a set of reverse order sliding windows from the one read of the packed input data from the storage.

12 . The method of claim 9 , wherein the executing the decoded single instruction routes the packed input data through the circuit according to the packed control data that generates a data path sequence or a coefficient sequence of a multiphase filter pattern from the one read of the packed input data from the storage.

13 . The method of claim 9 , wherein the executing the decoded single instruction routes the packed input data through the circuit according to the packed control data to select every other element of the packed input data as the respective inputs of the circuit, and generates a data path sequence of a set of sliding windows from the every other element of the packed input data.

14 . The method of claim 9 , wherein the executing the decoded single instruction routes the packed input data through the circuit according to the packed control data that generates a data path sequence of irregularly spaced samples from the one read of the packed input data from the storage.

15 . The method of claim 9 , wherein the executing the decoded single instruction routes the packed input data through the circuit according to the packed control data in a first mode for real numbers and in a second, different mode for complex numbers.

16 . The method of claim 9 , further comprising executing a plurality of instances of the single instruction in a same software loop, wherein the packed input data and the packed control data are passed to the plurality of instances of the single instruction through a pre-computed header.

17 . A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding a single instruction with a decoder of a processor into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and executing the decoded single instruction with an execution unit of the processor to:
send the packed control data to respective control inputs of a circuit that compr

Assignees

• Intel Corp

Inventors

• Chen Jian-Guo
• Dougherty David T
• Pinault Steven
• Venkataraghavan Parakalan
• Williams Joseph
• Yu Meng-Lin
• Azadet Kamran

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• H04L49/201 Primary

  Multicast operation; Broadcast operation · CPC title