Semiconductor chip and semiconductor package including bonding layers having alignment marks

Patent metadata

Field	Value
Publication number	US-12489071-B2
Application number	US-202217873990-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Oct 14, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip, wherein the first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer, the first external marks including a first pattern that is a first center portion and second pattern that is a first ring portion surrounding the first center portion when viewed from a plan view, the first center portion and first ring portion separated by a first gap, and a first internal marks within the first internal insulating layer, the first internal mark formed between the first center portion and the first ring portion from the plan view, wherein the first external marks and first internal marks together form a first alignment structure, and wherein the second bonding layer includes a second outermost insulating layer providing the second outer surface, a second internal insulating layer stacked between the second outermost insulating layer and the second substrate, second external marks disposed in the second outermost insulating layer, the second external marks including a third pattern that is a second center portion and fourth pattern that is a second ring portion surrounding the second center portion when viewed from a plan view, the second center portion and second ring portion separated by a second gap, and a second internal mark within the second internal insulating layer, the second internal mark formed between the second center portion and the second ring portion when viewed from the plan view, wherein the second external marks and second internal marks together form a second alignment structure.

2 . The semiconductor package of claim 1 , wherein the first external marks contact the second external marks, respectively.

3 . The semiconductor package of claim 1 ,
wherein, in a direction perpendicular to the first outer surface of the first semiconductor chip the first internal marks is disposed to overlap the first gap between the first center portion and first ring portion of the first external marks, and wherein, in a direction perpendicular to the second outer surface of the second semiconductor chip, the second internal mark is disposed to overlap the second gap between the second center portion and second ring portion of the second external marks.

4 . The semiconductor package of claim 3 ,
wherein the first internal mark has a width equal to or greater than a width of the first gap in a direction parallel to the first outer surface of the first semiconductor chip, and wherein the second internal mark has a width equal to or greater than a width of the second gap in a direction parallel to the second outer surface of the second semiconductor chip.

5 . The semiconductor package of claim 1 , wherein outer surfaces of the first external marks and an outer surface of the first internal mark are directed toward the second outer surface of the second semiconductor chip, and are combined to form the first alignment structure having a predetermined projected planar shape.

6 . The semiconductor package of claim 5 , wherein the predetermined projected planar shape is projected onto a plane parallel to the first outer surface of the first semiconductor chip, and has a diameter or a width in a direction parallel to the first outer surface of the first semiconductor chip of 10 μm or more.

7 . The semiconductor package of claim 5 , wherein outer surfaces of the second external marks and the outer surface of the second internal mark are directed toward the first outer surface of the first semiconductor chip, and are combined to form the second alignment structure having a projected planar shape corresponding to the first alignment structure.

8 . The semiconductor package of claim 1 ,
wherein the first external marks occupy a planar area larger than a planar area occupied by the first internal mark on a plane parallel to the first outer surface of the first semiconductor chip, and wherein the second external marks occupy a planar area larger than a planar area occupied by the second internal mark on a plane parallel to the second outer surface of the second semiconductor chip.

9 . The semiconductor package of claim 1 ,
wherein the first bonding layer further includes a first external pad disposed in the first outermost insulating layer and spaced apart from the first external marks, and wherein the second bonding layer further includes a second external pad disposed in the second outermost insulating layer and spaced apart from the second external marks.

10 . The semiconductor package of claim 1 , wherein the first external marks are electrically isolated from any active or passive circuit components of the first semiconductor chip, and the second external marks are electrically isolated from any active or passive circuit components of the second semiconductor chip.

11 . A semiconductor package, comprising:
a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having an upper surface provided by the first bonding layer; and a second semiconductor chip disposed on the upper surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed below the second substrate, and having a lower surface provided by the second bonding layer and in contact with the upper surface of the first semiconductor chip, wherein the first bonding layer includes first external marks and a first external pad providing the upper surface, the first external marks and the first external pad electrically insulated from each other, and the first external marks include concentric portions that include a center portion and a ring portion surrounding the center portion with a gap between the center portion and the ring portion, wherein the second bonding layer includes second external marks and a second external pad providing the lower surface, the second external marks and the second external pad electrically insulated from each other, and the second external marks include concentric portions that include a center portion and a ring portion surrounding the center portion with a gap between the center portion and the ring portion, and wherein a difference between a width in a first horizontal direction of the first external marks and a width in the first horizontal direction of the first external pad is 20% or less and a difference between a width in the first horizontal direction of the second external marks and a width in the first horizontal direction of the second external pad is 20% or less.

12 . The semiconductor package of claim 11 ,
wherein each of the first external marks has a width in the first horizontal direction the same as the width in the first horizontal direction of the first external pad, and wherein each of the second external marks has a width in the first horizontal direction the same as the width in the first horizontal direction of the second external pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyoeun
• KIM Juhyeon
• Lee Wonil
• Jee Youngkun

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/163

  using active alignment, e.g. detecting marks and correcting position · CPC title