Configuration file generation for fracturable data path in a coarse-grained reconfigurable processor

Patent metadata

Field	Value
Publication number	US-12487802-B2
Application number	US-202418583845-A
Country	US
Kind code	B2
Filing date	Feb 21, 2024
Priority date	Jan 20, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A compiler generates a configuration file to configure a fracturable data path in a coarse-grained reconfigurable processor. The configuration file, when loaded into the reconfigurable processor enables a fracturable data path in a configurable unit of the reconfigurable processor to produce multiple independent address sequences by analyzing two address calculations to determine the number of pipeline stages for each calculation. The configuration file includes first and second configuration data for distinct sets of computational stages within the pipelined computation stages, allowing the processor to generate a first address sequence using N pipeline stages and a second address sequence using M pipeline stages, where N and M are positive integers.

First claim

The invention claimed is:

1 . A non-transitory machine-readable medium comprising computer instructions that, in
response to being executed by a processor, cause the processor to produce a configuration file to configure a fracturable data path of a configurable unit in an array of configurable units of a coarse-grained reconfigurable processor to generate a plurality of independent address sequences including a first address sequence generated using a first address calculation and a second address sequence generated using a second address calculation, the fracturable data path comprising a plurality of pipelined computation stages, the configuration file produced by:
analyzing the first address calculation and the second address calculation to determine to use N pipeline stages for the first address calculation and M pipeline stages for the second address calculation, wherein N and M are positive integers;
generating first configuration data for a first set of stages to produce the first address sequence and second configuration data for a second set of stages to generate the second address sequence, the first set of stages consisting of N computational stages of the plurality of pipelined computation stages and the second set of stages consisting of M computational stages of the plurality of pipelined computation stages; and
including the first configuration data and the second configuration data in the configuration file.

2 . The non-transitory machine-readable medium of claim 1 , wherein the configuration file includes two or more immediate values for use in at least one computation stage of the first set of stages and second set of stages in the configuration file.

3 . The non-transitory machine-readable medium of claim 1 , wherein the first set of stages and the second set of stages are disjoint sets of contiguous stages of the plurality of pipelined computation stages.

4 . The non-transitory machine-readable medium of claim 1 , the fracturable data path of the configurable unit including an input, and each of the plurality of pipelined computation stages of the fracturable data path further including a respective pipeline register, arithmetic logic unit (ALU) and selection logic to select two or more operands for the its ALU;
the first set of stages including a first starting stage and a first ending stage and the second set of stages including a second starting stage and a second ending stage; the computer instructions further causing the processor to produce the configuration file to configure the selection logic of the first ending stage and second ending stage respectively to select operands for their respective ALU from outputs of the pipeline register of an immediately preceding stage, the input, or two or more immediate values associated with that stage from the configuration file; and to configure the selection logic in the first starting stage and the second starting stage respectively to select operands for the respective ALU from the input, or the two or more immediate values associated with that stage, but not from the outputs of the pipeline register of the immediately preceding stage.

5 . The non-transitory machine-readable medium of claim 4 , wherein the respective ALU of each of the plurality of pipelined computation stages each are capable to perform both signed and unsigned arithmetic.

6 . The non-transitory machine-readable medium of claim 4 , the input comprising a first portion coupled to a scalar bus of the array of configurable units, a second portion coupled to a lane of a vector bus of the array of configurable units, and a third portion coupled to a counter of the configurable unit;
the fracturable data path of the configurable unit including a first output, a second output, and a third output; the computer instructions further causing the processor to produce the configuration file by determining that one of the first portion, the second portion, or the third portion of the input directly provides a third address sequence and producing the configuration file to: select data from an output of an ending stage of the first set of stages to provide on the first output; select data from an output of an ending stage of the second set of stages to provide on the second output; and select an output of a header input register coupled to the determined one of the first portion, the second portion, or the third portion of the input to provide on the third output.

7 . The non-transitory machine-readable medium of claim 4 , wherein the respective ALU of each of the plurality of pipelined computation stages have a first input, a second input, and a third input.

8 . The non-transitory machine-readable medium of claim 1 , the fracturable data path of the configurable unit having two or more sub-paths with pipeline registers in each of the plurality of pipelined computation stages broken into sub-path pipeline registers, and including a first output and a second output respectively configurable to selectively provide data from one sub-path pipeline register of the plurality of pipelined computation stages;
the computer instructions further causing the processor to produce the configuration file to configure the first output to select data from a sub-path pipeline register of an ending stage of the first set of stages, and to configure the second output to select data from a sub-path pipeline register of an ending stage of the second set of stages.

9 . The non-transitory machine-readable medium of claim 8 , the configurable unit further comprising a multi-port memory having a first address input associated with a first access port of the multi-port memory and a second address input associated with a second access port of the multi-port memory, the first address input coupled to the first output of the fracturable data path and the second address input coupled to the second output of the fracturable data path;
the computer instructions further causing the processor to produce the configuration file to configure the multi-port memory to execute a first operation using the first access port and a second operation using the second access port.

10 . The non-transitory machine-readable medium of claim 1 , wherein the first address sequence includes meta data for memory accesses.

11 . A method for producing a configuration file to configure a fracturable data path of a configurable unit in an array of configurable units of a coarse-grained reconfigurable processor to generate a plurality of independent address sequences including a first address sequence generated using a first address calculation and a second address sequence generated using a second address calculation, the fracturable data path comprising a plurality of pipelined computation stages, the method comprising:
analyzing the first address calculation and the second address calculation to determine to use N pipeline stages for the first address calculation and M pipeline stages for the second address calculation, wherein N and M are positive integers; generating first configuration data for a first set of stages to produce the first address sequence and second configuration data for a second set of stages to generate the second address sequence, the first set of stages consisting of N computational stages of the plurality of pipelined computation stages and the second set of stages consisting of M computational stages of the plurality of pipelined computation stages; and including the first configuration data and the second configuration data in the configuration file.

12 . The method of claim 11 , wherein the configuration file includes two or more immediate values for use

Assignees

• Sambanova Systems Inc

Inventors

• Prabhakar Raghu
• Jackson David Brian
• Burson Scott

Classifications

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F8/441 Primary

  Register allocation; Assignment of physical memory space to logical memory space · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title