Compiler for a fracturable data path in a reconfigurable data processor

Patent metadata

Field	Value
Publication number	US-11928445-B2
Application number	US-202318099214-A
Country	US
Kind code	B2
Filing date	Jan 19, 2023
Priority date	Jan 20, 2022
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A complier produces a configuration file to configure a fracturable data path of a configurable unit in a coarse-grained reconfigurable processor to concurrently generate different address sequences generated using different address associated with different operations. The fracturable data path includes multiple computation stages respectively including a pipeline register. The compiler analyzes a first address calculation and a second address calculation and assigns a first set of stages to the first operation to generate the first address sequence and a second set of stages to the second operation to generate the second address sequence using the second set of stages, based on the analysis. A configuration file for the configurable unit is generated by the compiler that assigns the first set of stages to the first operation and the second set of stages to the second operation and includes two or more immediate values for each computation stage.

First claim

The invention claimed is:

1. A non-transitory machine-readable medium comprising computer instructions that, in response to being executed by a processor, cause the processor to:
produce a configuration file to configure a fracturable data path of a configurable unit in an array of configurable units of a coarse-grained reconfigurable processor to generate a plurality of address sequences including a first address sequence generated using a first address calculation and a second address sequence generated using a second address calculation, the first address calculation associated with a first operation of a plurality of independent operations of the configurable unit and the second address calculation associated with a second operation of the plurality of independent operations of the configurable unit, the fracturable data path of the configurable unit comprising a plurality of computation stages respectively including a pipeline register, the configuration file produced by:
analyzing the first address calculation and the second address calculation;
assigning a first set of stages of the plurality of computation stages to the first operation to generate the first address sequence using the first set of stages based on said analysis;
assigning a second set of stages of the plurality of computation stages to the second operation to generate the second address sequence using the second set of stages based on said analysis; and
including two or more immediate values for each computation stage of the first set of stages and second set of stages in the configuration file.

2. The non-transitory machine-readable medium of claim 1 , the fracturable data path of the configurable unit including an input, and the plurality of computation stages of the fracturable data path further including respective arithmetic logic units (ALUs) and selection logic to select two or more operands for the respective ALU;
the first set of stages including a first starting stage and a first ending stage and the second set of stages including a second starting stage and a second ending stage;
the instructions further causing the processor to produce the configuration file to configure the selection logic of the first ending stage and second ending stage respectively to select operands for the respective ALU from outputs of the pipeline register of an immediately preceding stage, the input, or the two or more immediate values associated with that stage; and
to configure the selection logic in the first starting stage and the second starting stage respectively to select operands for the respective ALU from the input, or the two or more immediate values associated with that stage, but not from the outputs of the pipeline register of the immediately preceding stage.

3. The non-transitory machine-readable medium of claim 2 , the input comprising:
a first portion coupled to a scalar bus of the array of configurable units;
a second portion coupled to a lane of a vector bus of the array of configurable units; and
a third portion coupled to a counter of the configurable unit.

4. The non-transitory machine-readable medium of claim 3 , the fracturable data path of the configurable unit including a first output, a second output, and a third output, and the instructions further causing the processor to produce the configuration file by:
determining that one of the first portion, the second portion, or the third portion of the input directly provides a third address sequence; and
producing the configuration file to:
select data from an output of an ending stage of the first set of stages to provide on the first output;
select data from an output of an ending stage of the second set of stages to provide on the second output; and
select an output of a header input register coupled to the determined one of the first portion, the second portion, or the third portion of the input to provide on the third output.

5. The non-transitory machine-readable medium of claim 2 , wherein the ALUs of the plurality of computation stages each have a first input, a second input, and a third input.

6. The non-transitory machine-readable medium of claim 5 , the selection logic of a stage of the plurality of computation stages configurable to provide a first immediate data value to the first input of the ALU of the stage and a second immediate data value to the second input of the ALU of the stage, wherein the two or more immediate values associated with the stage include the first immediate data value and the second immediate data value.

7. The non-transitory machine-readable medium of claim 2 , wherein the first set of stages and the second set of stages are disjoint.

8. The non-transitory machine-readable medium of claim 2 , wherein at least one of the first set of stages and the second set of stages consists of a single stage of the plurality of computation stages.

9. The non-transitory machine-readable medium of claim 2 , the fracturable data path including two or more sub-paths and the pipeline registers of the plurality of computation stages broken into sub-path pipeline registers; and
the instructions further causing the processor to produce the configuration file by:
determining a first ALU operation of the first address calculation for the first starting stage;
selecting a first sub-path to use for a value by the ALU of the first starting stage;
determining a second ALU operation of the first address calculation for the first ending stage;
selecting a second sub-path to use for a value by the ALU of the first ending stage; and

the instructions further causing the processor to produce the configuration file to:
configure the ALU of the starting stage to perform the first ALU operation and direct a result of the first ALU operation to a sub-path pipeline register of the first starting stage associated with the first sub-path; and
configure the ALU of the first ending stage to perform the second ALU operation and direct a result of the second ALU operation to a sub-path pipeline register of the first ending stage associated with the second sub-path.

10. The non-transitory machine-readable medium of claim 1 , the fracturable data path of the configurable unit having two or more sub-paths with the pipeline registers of the plurality of computation stages broken into sub-path pipeline registers, and including a first output and a second output respectively configurable to selectively provide data from one sub-path pipeline register of the plurality of computation stages; and
the instructions further causing the processor to produce the configuration file to configure the first output to select data from a sub-path pipeline register of an ending stage of the first set of stages, and to configure the second output to select data from a sub-path pipeline register of an ending stage of the second set of stages.

11. The non-transitory machine-readable medium of claim 10 , the configurable unit further comprising a multi-port memory having a first address input associated with a first access port of the multi-port memory and a second address input associated with a second access port of the multi-port memory, the first address input coupled to the first output of the fracturable data path and the second address input coupled to the second output of the fracturable data path; and
the instructions further causing the processor to produce the configuration file to configure the multi-port memory to execute the first operation using the first access port and the second operation using the second access port.

12. The non-transitory machine-readable medium of claim 11 , the fracturable data path further comprising a thir

Assignees

• Sambanova Systems Inc

Inventors

• Prabhakar Raghu
• Jackson David Brian
• Burson Scott

Classifications

• G06F8/441 Primary

  Register allocation; Assignment of physical memory space to logical memory space · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F9/3897 Primary

  with adaptable data path · CPC title