Systems and Methods for Using Error Correction and Pipelining Techniques for an Access Triggered Computer Architecture
US-2017364340-A1 · Dec 21, 2017 · US
Register allocation; Assignment of physical memory space to logical memory space
Register allocation; Assignment of physical memory space to logical memory space · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F8/441 |
| Official title | {Register allocation; Assignment of physical memory space to logical memory space} |
| Display label | Register allocation; Assignment of physical memory space to logical memory space |
| Total patents | 346 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 21 |
| 2016 | 22 |
| 2017 | 34 |
| 2018 | 29 |
| 2019 | 37 |
| 2020 | 35 |
| 2021 | 39 |
| 2022 | 29 |
| 2023 | 42 |
| 2024 | 26 |
| 2025 | 21 |
| 2026 | 11 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Method and apparatus for performing register allocation
US-9841975-B2 · Dec 12, 2017 · US
Processor that includes a special store instruction used in regions of a computer program where memory aliasing may occur
US-2017351496-A1 · Dec 7, 2017 · US
Data processing method, computer readable medium and data processing device
US-9836408-B2 · Dec 5, 2017 · US
Reconfiguration of address space based on loading short pointer mode application
US-9836291-B1 · Dec 5, 2017 · US
Directed Placement of Data in Memory
US-2017315755-A1 · Nov 2, 2017 · US
Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
US-9785423-B2 · Oct 10, 2017 · US
Relaxing user-specified register constraints for improving register allocation
US-2017286078-A1 · Oct 5, 2017 · US
Compiler for translating between a virtual image processor instruction set architecture (isa) and target hardware having a two-dimensional shift array structure
US-2017242669-A1 · Aug 24, 2017 · US
Allocating register halves independently
US-9696975-B2 · Jul 4, 2017 · US
Systems and methods for register allocation
US-9690584-B2 · Jun 27, 2017 · US
Efficient error handling mechanisms in data storage systems
US-9626118-B2 · Apr 18, 2017 · US
Memory-aware matrix factorization
US-9626107-B2 · Apr 18, 2017 · US
Memory-aware matrix factorization
US-9626736-B2 · Apr 18, 2017 · US
Conditional stack frame allocation
US-2017090812-A1 · Mar 30, 2017 · US
Advanced interactive command-line front-end for graph analysis systems
US-9575736-B2 · Feb 21, 2017 · US
Allocation method, apparatus, and program for managing architectural registers and physical registers using mapping tables
US-2017024214-A1 · Jan 26, 2017 · US
Memory-aware matrix factorization
US-2016371005-A1 · Dec 22, 2016 · US
Memory-aware matrix factorization
US-2016371809-A1 · Dec 22, 2016 · US
Allocation of alias registers in a pipelined schedule
US-9495168-B2 · Nov 15, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F8/441?
- CPC G06F8/441 is the Cooperative Patent Classification code for “Register allocation; Assignment of physical memory space to logical memory space.”
- How many patents are filed under CPC G06F8/441 (Register allocation; Assignment of physical memory space to logical memory space)?
- Our database includes 346 publications tagged with this CPC code.
- Is patent activity under CPC G06F8/441 growing?
- Publication counts under this code: 26 in 2024 vs 21 in 2025 (latest complete years).