Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)

Patent metadata

Field	Value
Publication number	US-9437501-B1
Application number	US-201514861326-A
Country	US
Kind code	B1
Filing date	Sep 22, 2015
Priority date	Sep 22, 2015
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

First claim

What is claimed is:

1. A method of making a nanowire device, the method comprising:
disposing a first nanowire stack of a first transistor over a substrate, the first nanowire stack comprising alternating layers of a first semiconducting material and a second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface of the first nanowire stack;
disposing a second nanowire stack of a second transistor over the substrate, the second nanowire stack comprising alternating layers of the first semiconducting material and the second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface of the second nanowire stack;
forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack;
oxidizing a portion of the first nanowire stack within the first gate spacer of the first gate region; and
removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

2. The method of claim 1 , wherein the first nanowire stack and the second nanowire stack are formed simultaneously before oxidizing a portion of the first nanowire stack.

3. The method of claim 1 , further comprising filling the first gate region and the second gate region with a high-k metal gate material.

4. The method of claim 1 , wherein the first semiconducting material comprises silicon germanium, and the second semiconducting material comprises silicon.

5. The method of claim 1 , wherein oxidizing a portion of the first nanowire stack comprises a gas cluster ion beam process.

6. The method of claim 1 , wherein oxidizing a portion of the first nanowire stack comprises a room temperature oxidation process.

7. The method of claim 1 , wherein oxidizing a portion of the first nanowire stack comprises bombarding the first nanowire stack with ionized oxygen atoms, ionized oxygen molecules, or a combination thereof.

8. A method of making a nanowire device, the method comprising:
disposing a first nanowire stack of a first transistor over a substrate, the first nanowire stack comprising alternating layers of a first semiconducting material and a second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface of the first nanowire stack;
disposing a second nanowire stack of a second transistor over the substrate, the second nanowire stack comprising alternating layers of the first semiconducting material and the second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface of the second nanowire stack;
forming a first gate on the first nanowire stack and a second gate on the second nanowire stack, the first and second gates comprising a sacrificial gate material;
removing the sacrificial gate material from the first gate and the second gate;
disposing a mask over the second transistor;
oxidizing a portion of the first nanowire stack;
removing the mask and the first semiconducting material from the first nanowire stack and the second nanowire stack; and
filling the first gate and the second gate with a high-k metal gate material.

9. The method of claim 8 , wherein the sacrificial gate material comprises amorphous silicon, polysilicon, or a combination thereof.

10. The method of claim 8 , wherein oxidizing a portion of the first nanowire stack comprises bombarding the first nanowire stack with ionized oxygen atoms, ionized oxygen molecules, or a combination thereof.

11. The method of claim 8 , wherein first semiconducting material comprises silicon germanium, and the second semiconducting material comprises silicon.

12. The method of claim 8 , wherein the first and second transistors comprise a different number of active nanowires.

13. A nanowire device, comprising:
a first transistor comprising a first gate disposed over a portion of a first nanowire stack, the first nanowire stack comprising a first semiconducting nanowire and a dielectric nanowire; and
a second transistor comprising a second gate disposed over a portion of a second nanowire stack, the second nanowire stack comprising a second semiconducting nanowire and a third semiconducting nanowire.

14. The nanowire device of claim 13 , wherein the first nanowire stack and the second nanowire stack are disposed over an oxide layer of a substrate.

15. The nanowire device of claim 13 , wherein the first, second, and third semiconducting nanowires comprise silicon, silicon germanium, or a combination thereof.

16. The nanowire device of claim 13 , wherein the dielectric nanowire comprises silicon dioxide.

17. The nanowire device of claim 13 , wherein the first transistor further comprises a source region and a drain region on opposing sides of the first gate.

18. The nanowire device of claim 17 , wherein the source region and the drain region comprise epitaxial growth disposed over the first nanowire stack.

19. The nanowire device of claim 18 , wherein the dielectric nanowire comprises a semiconducting portion beneath the epitaxial growth.

20. The nanowire device of claim 13 , wherein the dielectric nanowire comprises a dielectric portion and a semiconducting portion, the semiconducting portion being disposed beneath an epitaxial growth forming a source/drain region.

Assignees

• IBM
• Globalfoundries Inc
• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Miao Xin
• Xie Ruilong
• Yamashita Tenko

Classifications

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P30/224

  of a cluster, e.g. using a gas cluster ion beam · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title