Semiconductor device package and methods of formation

Patent metadata

Field	Value
Publication number	US-12482763-B2
Application number	US-202217814997-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Jul 26, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A laser grooving operation is performed to form a plurality of grooves in a semiconductor die prior to attaching the semiconductor die to a semiconductor device package substrate. In addition to forming a first groove through which blade sawing is to be performed to separate the semiconductor die from other semiconductor dies, a second groove may be formed between the first groove and a seal ring of the semiconductor die. The second groove is configured to contain any potential delamination that might otherwise propagate to an active region of the semiconductor die. Accordingly, the second groove and the associated laser grooving operation described herein may reduce the likelihood of delamination that might otherwise be caused by swelling and/or expansion in a molding compound formed around the semiconductor die after the semiconductor die is attached to the semiconductor device package substrate.

First claim

What is claimed is:

1 . A method, comprising:
forming a first semiconductor die package and a second semiconductor die package, side-by-side with the first semiconductor die package, on a wafer; forming a first groove in a scribe line region between the first semiconductor die package and the second semiconductor die package; forming a second groove in the scribe line region; forming a third groove in the scribe line region,
wherein the second groove is adjacent to a first side of the first groove that faces the first semiconductor die package,
wherein the third groove is adjacent to a second side of the first groove that faces the second semiconductor die package,
wherein a width of the first groove is greater relative to a width of the second groove, and
wherein the width of the first groove is greater relative to a width of the third groove;
cutting through a bottom of the first groove to separate the first semiconductor die package and the second semiconductor die package; mounting the first semiconductor die package to a carrier substrate; and depositing a molding compound around the first semiconductor die package,
wherein the molding compound fills in the second groove to form a stress relief trench in the first semiconductor die package.

2 . The method of claim 1 , wherein forming the second groove comprises:
forming the second groove prior to forming the first groove; and wherein forming the third groove comprises:
forming the third groove prior to forming the first groove.

3 . The method of claim 1 , wherein forming the second groove comprises:
forming the second groove after forming the first groove; and wherein forming the third groove comprises:
forming the third groove after forming the first groove.

4 . The method of claim 1 , wherein forming the second groove comprises:
forming the second groove prior to forming the first groove; and wherein forming the third groove comprises:
forming the third groove after forming the first groove.

5 . The method of claim 1 , further comprising:
forming a plurality of through integrated fanout (InFO) vias (TIVs) of a semiconductor device package adjacent to one or more sides of the first semiconductor die package; and depositing the molding compound around the plurality of TIVs.

6 . The method of claim 5 , further comprising:
performing one or more reliability tests on the semiconductor device package,
wherein the stress relief trench resists a transfer of stress, from the molding compound to the semiconductor device package, that results from swelling of the molding compound during the one or more reliability tests.

7 . The method of claim 1 , wherein forming the second groove comprises:
forming the second groove to a width that is included in a range of microns to 20 microns.

8 . A method, comprising:
forming a first semiconductor die package and a second semiconductor die package on a wafer; forming a first groove, a second groove, and a third groove between the first semiconductor die package and the second semiconductor die package,
wherein the first groove is between the second groove and the third groove;
cutting through a full thickness of the wafer via the first groove to separate the first semiconductor die package and the second semiconductor die package; mounting the first semiconductor die package to a carrier substrate; and depositing a molding compound around the first semiconductor die package,
wherein the molding compound fills in the second groove to form a stress relief trench in the first semiconductor die package.

9 . The method of claim 8 , wherein a width of the first groove is greater than a width of the second groove.

10 . The method of claim 8 , wherein a width of the first groove is greater than a width of the third groove.

11 . The method of claim 8 , wherein a width of the first groove is greater than 30 microns.

12 . The method of claim 8 , wherein the first groove is formed through a connection structure of the wafer and into a portion of a semiconductor die of the wafer.

13 . The method of claim 8 , wherein the first groove is formed through an insulator layer of the wafer, a connection structure of the wafer, and into a portion of a semiconductor die of the wafer.

14 . The method of claim 8 , wherein the second groove is formed through a connection structure of the wafer and into a portion of a semiconductor die of the wafer.

15 . A system, comprising:
one or more semiconductor processing tool sets configured to:
form a first semiconductor die package and a second semiconductor die package, side-by-side with the first semiconductor die package, on a wafer;
form a first groove in a scribe line region between the first semiconductor die package and the second semiconductor die package;
form a second groove in the scribe line region;
form a third groove in the scribe line region,
wherein the second groove is adjacent to a first side of the first groove that faces the first semiconductor die package,
wherein the third groove is adjacent to a second side of the first groove that faces the second semiconductor die package,
wherein a width of the first groove is greater relative to a width of the second groove, and
wherein the width of the first groove is greater relative to a width of the third groove;

cut through a bottom of the first groove to separate the first semiconductor die package and the second semiconductor die package;
mount the first semiconductor die package to a carrier substrate; and
deposit a molding compound around the first semiconductor die package,
wherein the molding compound fills in the second groove to form a stress relief trench in the first semiconductor die package.

16 . The system of claim 15 , wherein the one or more semiconductor processing tool sets, to form the second groove, are configured to:
form the second groove prior to the first groove being formed; and wherein the one or more semiconductor processing tool sets, to form the third groove, are configured to:
form the third groove prior to the first groove being formed.

17 . The system of claim 15 , wherein the one or more semiconductor processing tool sets, to form the second groove, are configured to:
form the second groove after the first groove is formed; and wherein the one or more semiconductor processing tool sets, to form the third groove, are configured to:
form the third groove after the first groove is formed.

18 . The system of claim 15 , wherein the one or more semiconductor processing tool sets, to form the second groove, are configured to:
form the second groove prior to the first groove being formed; and wherein the one or more semiconductor processing tool sets, to form the third groove, are configured to:
form the third groove after the first groove is formed.

19 . The system of claim 15 , wherein the one or more semiconductor processing tool sets are further configured to:
form a plurality of through integrated fanout (InFO) vias (TIVs) of a semiconductor device package adjacent to one or more sides of the first semiconductor die package; and deposit the molding compound around the plurality of TIVs.

20 . The system of claim 19 , wherein the one or more semiconductor processing tool sets are further configured to:
perform one or more reliability tests on the semiconductor device package,
wherein the stress relief trench is configured to resist a transfer of stress, from the molding co

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Tien-Chung
• Huang Li-Hsien
• Wu Ming-Feng
• Liu Yung-Sheng
• Chen Chun-Jen
• He Jun

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title