Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12477733-B2
Application number	US-202217929454-A
Country	US
Kind code	B2
Filing date	Sep 2, 2022
Priority date	Mar 16, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A semiconductor memory device according to an embodiment includes a stacked body in which a gate electrode layer and a first insulating layer are alternately stacked in a first direction, a semiconductor layer in the stacked body and extending in the first direction, a second insulating layer between the semiconductor layer and the stacked body, a third insulating layer provided between the second insulating layer and the stacked body, and a first layer between the second insulating layer and the third insulating layer. The first layer contains silicon and nitrogen and includes a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region contains or does not contain fluorine, the second region contains fluorine, and a fluorine concentration of the second region is higher than a fluorine concentration of the first region.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a stacked body in which a gate electrode layer and a first insulating layer are alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a second insulating layer provided between the semiconductor layer and the stacked body; a third insulating layer provided between the second insulating layer and the stacked body; a first layer provided between the second insulating layer and the third insulating layer, the first layer containing silicon (Si) and nitrogen (N), the first layer including a first region between the gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region containing or not containing fluorine (F), the second region containing fluorine (F), and a fluorine concentration of the second region being higher than a fluorine concentration of the first region; and a fourth insulating layer provided between the gate electrode layer and the third insulating layer and between the gate electrode layer and the first insulating layer, the fourth insulating layer including a third region between the gate electrode layer and the third insulating layer and a fourth region between the gate electrode layer and the first insulating layer, the third region containing or not containing fluorine (F), the fourth region containing fluorine (F), and a fluorine concentration of the fourth region being higher than a fluorine concentration of the third region.

2 . The semiconductor memory device according to claim 1 , wherein the fluorine concentration of the second region is equal to or less than 1×10 20 atoms/cm 3 .

3 . The semiconductor memory device according to claim 1 , wherein an atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first layer is equal to or more than 1.2.

4 . The semiconductor memory device according to claim 1 , wherein an atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first region is larger than an atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the second region.

5 . The semiconductor memory device according to claim 4 , wherein the atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first region is equal to or more than 1.25, and the atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the second region is equal to or more than 1.2 and less than 1.25.

6 . The semiconductor memory device according to claim 1 , wherein the first insulating layer contains fluorine.

7 . The semiconductor memory device according to claim 1 , wherein
the first insulating layer contains silicon (Si) and oxygen (O), and the fourth insulating layer contains aluminum (Al) and oxygen (O).

8 . The semiconductor memory device according to claim 1 , wherein the third insulating layer contains a ferroelectric material at least in a region between the first insulating layer and the first layer.

9 . The semiconductor memory device according to claim 8 , wherein the third insulating layer contains a paraelectric material in a region between the gate electrode layer and the first layer.

10 . A semiconductor memory device comprising:
a first gate electrode layer extending in a first direction; a second gate electrode layer extending in the first direction and adjacent to the first gate electrode layer in a second direction crossing the first direction; a semiconductor layer provided between the first gate electrode layer and the second gate electrode layer, and extending in a third direction crossing the first direction and the second direction; a third gate electrode layer extending in the first direction and adjacent to the first gate electrode layer in the third direction; a first insulating layer provided between the first gate electrode layer and the third gate electrode layer; a second insulating layer provided between the semiconductor layer and the first gate electrode layer and between the semiconductor layer and the first insulating layer; a third insulating layer provided between the second insulating layer and the first gate electrode layer and between the second insulating layer and the first insulating layer; a first layer provided between the second insulating layer and the third insulating layer, the first layer containing silicon (Si) and nitrogen (N), the first layer including a first region between the first gate electrode layer and the semiconductor layer and a second region between the first insulating layer and the semiconductor layer, the first region containing or not containing fluorine (F), the second region containing fluorine (F), and a fluorine concentration of the second region being higher than a fluorine concentration of the first region; and a fourth insulating layer provided between the first gate electrode layer and the third insulating layer and between the first gate electrode layer and the first insulating layer, the fourth insulating layer including a fifth region between the first gate electrode layer and the third insulating layer and a sixth region between the first gate electrode layer and the first insulating layer, the fifth region containing or not containing fluorine (F), and the sixth region containing fluorine (F), and a fluorine concentration of the sixth region being higher than a fluorine concentration of the fifth region.

11 . The semiconductor memory device according to claim 10 , wherein the fluorine concentration of the second region is equal to or less than 1×10 20 atoms/cm 3 .

12 . The semiconductor memory device according to claim 10 , wherein an atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first layer is equal to or more than 1.2.

13 . The semiconductor memory device according to claim 10 , wherein an atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first region is larger than an atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the second region.

14 . The semiconductor memory device according to claim 13 , wherein the atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first region is equal to or more than 1.25, and the atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the second region is equal to or more than 1.2 and less than 1.25.

15 . The semiconductor memory device according to claim 10 , wherein the first insulating layer contains fluorine.

16 . The semiconductor memory device according to claim 10 , wherein the first layer further includes a third region between the second gate electrode layer and the semiconductor layer and a fourth region between the first region and the third region,
the third region contains or does not contain fluorine (F), the fourth region contains fluorine (F), and a fluorine concentration of the fourth region is higher than a fluorine concentration of the first region, and the fluorine concentration of the fourth region is higher than a fluorine concentration of the third region.

17 . The semiconductor memory device according to claim 10 , wherein
the first insulating layer contains silicon (Si) and oxygen (O), and the fourth insulating layer contains aluminum (Al) and oxygen (O).

18 . The semiconductor memory device according to claim 10 , further comprising:
a fifth insulating layer provided between the first gate electrode layer and the second gate electrode layer, wherein the fourth insulating layer further includes a seventh region between the first gate electrode layer and the fifth insulating layer, the seventh regi

Assignees

• Kioxia Corp

Inventors

• Seki Harumi
• Suzuki Masamichi
• Tanaka Reika
• Ota Kensuke
• Higashi Yusuke

Classifications

• H10D64/689 Primary

  having ferroelectric layers · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B51/10

  characterised by the top-view layout · CPC title

• H10B51/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title