Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11737281-B2
Application number	US-202117645133-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Jun 17, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a first insulating layer between the semiconductor layer and the first gate electrode layer; a second insulating layer between the first insulating layer and the first gate electrode layer, the second insulating layer having a first portion containing a ferroelectric material; and a first layer between the first insulating layer and the second insulating layer, the first layer containing silicon, nitrogen, and fluorine, the first layer having a first region and a second region between the first region and the second insulating layer, the first layer having a second atomic ratio of nitrogen to silicon in the second region higher than a first atomic ratio of nitrogen to silicon in the first region, and the first layer having fluorine concentration higher than the second region.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor layer extending in a first direction;
a first gate electrode layer;
a first insulating layer provided between the semiconductor layer and the first gate electrode layer;
a second insulating layer provided between the first insulating layer and the first gate electrode layer, and the second insulating layer including a first portion containing a ferroelectric material; and
a first layer provided between the first insulating layer and the second insulating layer, the first layer containing silicon (Si), nitrogen (N), and fluorine (F), the first layer including a first region and a second region provided between the first region and the second insulating layer, a second atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the second region being higher than a first atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first region, and a first fluorine concentration in the first region being higher than a second fluorine concentration in the second region.

2. The semiconductor memory device according to claim 1 , wherein the first atomic ratio is equal to or less than 1.25, and the second atomic ratio is more than 1.25.

3. The semiconductor memory device according to claim 1 , wherein the first fluorine concentration is equal to or more than 2×10 20 atoms/cm 3 , and the second fluorine concentration is equal to or less than 1×10 20 atoms/cm 3 .

4. The semiconductor memory device according to claim 1 , wherein the first insulating layer contains silicon (Si), nitrogen (N), and oxygen (O).

5. The semiconductor memory device according to claim 4 , wherein the first insulating layer contains fluorine (F).

6. The semiconductor memory device according to claim 1 , wherein the second insulating layer contains oxygen (O) and at least one metal element of hafnium (Hf) or zirconium (Zr).

7. The semiconductor memory device according to claim 1 , wherein the second region is in contact with the second insulating layer.

8. The semiconductor memory device according to claim 1 , further comprising:
a second gate electrode layer provided apart from the first gate electrode layer in the first direction; and
a third insulating layer provided between the first gate electrode layer and the second gate electrode layer.

9. The semiconductor memory device according to claim 8 , wherein the second insulating layer is provided between the first gate electrode layer and the third insulating layer.

10. The semiconductor memory device according to claim 8 , wherein the second insulating layer further includes a second portion provided between the semiconductor layer and the third insulating layer, and the second portion contains a paraelectric material.

11. A semiconductor memory device comprising:
a semiconductor layer extending in a first direction;
a first gate electrode layer;
a first insulating layer provided between the semiconductor layer and the first gate electrode layer;
a second insulating layer provided between the first insulating layer and the first gate electrode layer, the second insulating layer containing oxygen (O) and at least one metal element of hafnium (Hf) or zirconium (Zr), the second insulating layer including a first portion, and a main constituent substance of the first portion being a crystal of an orthorhombic crystal system or a crystal of a trigonal crystal system; and
a first layer provided between the first insulating layer and the second insulating layer, the first layer containing silicon (Si), nitrogen (N), and fluorine (F), the first layer including a first region and a second region provided between the first region and the second insulating layer, a second atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the second region being higher than a first atomic ratio (N/Si) of nitrogen (N) to silicon (Si) in the first region, and a first fluorine concentration in the first region being higher than a second fluorine concentration in the second region.

12. The semiconductor memory device according to claim 11 , wherein the first atomic ratio is equal to or less than 1.25, and the second atomic ratio is more than 1.25.

13. The semiconductor memory device according to claim 11 , wherein the first fluorine concentration is equal to or more than 2×10 20 atoms/cm 3 , and the second fluorine concentration is equal to or less than 1×10 20 atoms/cm 3 .

14. The semiconductor memory device according to claim 11 , wherein the first insulating layer contains silicon (Si), nitrogen (N), and oxygen (O).

15. The semiconductor memory device according to claim 14 , wherein the first insulating layer contains fluorine (F).

16. The semiconductor memory device according to claim 11 , wherein the first portion contains a ferroelectric material.

17. The semiconductor memory device according to claim 11 , wherein the second region is in contact with the second insulating layer.

18. The semiconductor memory device according to claim 11 , further comprising:
a second gate electrode layer provided apart from the first gate electrode layer in the first direction; and
a third insulating layer provided between the first gate electrode layer and the second gate electrode layer.

19. The semiconductor memory device according to claim 18 , wherein the second insulating layer is provided between the first gate electrode layer and the third insulating layer.

20. The semiconductor memory device according to claim 18 , wherein the second insulating layer further includes a second portion provided between the semiconductor layer and the third insulating layer, and a main constituent substance of the second portion is a crystal other than crystals of an orthorhombic crystal system and a trigonal crystal system.

Assignees

• Kioxia Corp

Inventors

• Seki Harumi
• Ota Kensuke
• Saitoh Masumi

Classifications

• H10D64/689

  having ferroelectric layers · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/30

  characterised by the memory core region · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title