Memory system, operating method of the same, and controller of memory device

Patent metadata

Field	Value
Publication number	US-12475966-B2
Application number	US-202318222563-A
Country	US
Kind code	B2
Filing date	Jul 17, 2023
Priority date	Jul 26, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A memory system including a memory device that receives a plurality of signals including a post package repair (PPR) command from a host, wherein the memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, and anti-fuse memory cells, and a PPR control circuit that transmits to the host whether a PPR operation on a defective memory cell of the memory cell array has passed.

First claim

What is claimed is:

1 . A memory system comprising a memory device configured to receive a plurality of signals including a post package repair command from a host,
wherein the memory device comprises: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines and a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, an anti-fuse array configured to store a plurality of data values related to at least one of a position of a defective memory cell, a row address for the defective memory cell, or dirty fuse data indicating whether each of the plurality of memory cells is defective; and a post package repair (PPR) control circuit configured to transmit to the host an indication of whether a PPR operation on the defective memory cell has passed, wherein the PPR control circuit is configured to:
determine a target which is an object of the PPR operation in the memory cell array,
compare a first data value stored in the anti-fuse array for the target before the PPR operation with a second data value stored in the anti-fuse array for the target after the PPR operation, to obtain a comparison result, and
determine whether the PPR operation has passed based on the comparison result.

2 . The memory system of claim 1 , wherein the PPR control circuit is configured to determine that the PPR operation has failed based on the second data value for the target after the PPR operation being equal to the first data value for the target before the PPR operation.

3 . The memory system of claim 2 , wherein the PPR control circuit is configured to transmit an alert signal to the host when the PPR operation has failed.

4 . The memory system of claim 3 , wherein the memory device is configured to receive a retry signal for retrying the PPR operation based on transmitting the alert signal.

5 . The memory system of claim 1 , wherein the PPR control circuit comprises a first transistor configured to receive the first data value of the target before the PPR operation as a first signal, a second transistor configured to receive the second data value of the target after the PPR operation as a second signal, and a logic gate configured to compare the first signal with the second signal.

6 . The memory system of claim 5 , wherein the logic gate comprises an XOR gate, and wherein the PPR control circuit is configured to generate a failure signal based on the first signal being equal to the second signal.

7 . The memory system of claim 1 , wherein the memory device further comprises normal fuse memory cells having different electrical characteristics from anti-fuse memory cells included in the anti-fuse array, and wherein the PPR control circuit is configured to perform the PPR operation on the normal fuse memory cells.

8 . An operating method of a memory system including a memory controller and a memory device including a memory cell array and an anti-fuse array, the memory cell array comprising a plurality of memory cells, the operating method comprising:
receiving, from a host, a request for a post package repair (PPR) operation on a defective memory cell of the memory cell array; performing the PPR operation responsive to the request the PPR operation by the host; and storing, in the anti-fuse array, a plurality of data values related to at least one of a position of the defective memory cell, a row address for the defective memory cell, or dirty fuse data indicating whether each of the plurality of memory cells is defective; wherein the performing of the PPR operation comprises:
determining a target which is an object of the PPR operation from the memory cell array;
comparing a first data value stored in the anti-fuse array for the target before the PPR operation and a second data value stored in the anti-fuse array for the target after the PPR operation, to obtain a comparison result; and
determining a status of the PPR operation as passed or failed based on the comparison result.

9 . The operating method of claim 8 , wherein the determining the status of the PPR operation comprises determining the status of the PPR operation is failed based on the comparison result indicating that the second data value for the target after the PPR operation is equal to the first data value for the target before the PPR operation.

10 . The operating method of claim 9 , comprising transmitting an alert signal to the host based on the status of the PPR operation being failed.

11 . The operating method of claim 10 , further comprising:
receiving, from the host, a retry signal for the PPR operation in response to the transmitting of the alert signal; and performing another PPR operation on the target responsive to the retry signal.

12 . The operating method of claim 8 , wherein the comparing the first data value and the second data value comprises:
receiving, by a first transistor, the first data value for the target before the PPR operation as a first input, and receiving, by a second transistor, the second data value for the target after the PPR operation as a second input; and comparing, by a logic gate, the first input with the second input.

13 . The operating method of claim 12 , wherein the logic gate is an XOR gate, and the determining the status of the PPR operation comprises generating a failure signal by the XOR gate based on the first input being equal to the second input.

14 . The operating method of claim 8 , wherein the performing the PPR operation further comprises performing the PPR operation on normal fuse memory cells having different electrical characteristics from anti-fuse memory cells included in the anti-fuse array.

15 . A controller of a memory device, the memory device comprising a memory cell array including a plurality of memory cells, an anti-fuse array storing a plurality of data values related to at least one a position of a defective memory cell, a row address for the defective memory cell, or dirty fuse data indicating whether each of the plurality of memory cells is defective, and a post package repair (PPR) control circuit, wherein the controller is disposed in a host distinct from the memory device,
the controller configured to: generate a PPR command signal requesting a PPR operation on the defective memory cell of the memory cell array which is a target for the PPR operation, transmit the PPR command signal to the memory device, and receive a performance result of the PPR operation on the target from a PPR control circuit of the memory device responsive to the PPR command signal, the performance result based on comparison of data values stored in the anti-fuse array for the target before and after-the PPR operation.

16 . The controller of claim 15 , wherein the controller is configured to transmit a retry signal to the memory device requesting a second PPR operation on the target based on the performance result.

17 . The controller of claim 15 , wherein the performance result indicates failure of the PPR operation based on a first data value for the target before the PPR operation being equal to a second data value for the target after the PPR operation.

18 . The controller of claim 15 , wherein the performance result indicates passing of the PPR operation based on a first data value for the target before the PPR operation being different from a second data value for the target after the PPR operation.

19 . The controller of claim 15 , wherein the controller

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Namhyung
• Kim Daejeong
• Kim Dohan
• Seo Deokho
• Song Jaein
• CHOI Insu

Classifications

• G11C29/1201

  comprising I/O circuitry · CPC title

• G11C29/027

  in fuses · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G11C29/808

  using a flexible replacement scheme · CPC title

• G11C29/787

  using a fuse hierarchy · CPC title