Post package repair for mapping to a memory failure pattern

Patent metadata

Field	Value
Publication number	US-10546649-B2
Application number	US-201515753315-A
Country	US
Kind code	B2
Filing date	Aug 18, 2015
Priority date	Aug 18, 2015
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

In one example in accordance with the present disclosure, a method includes mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device, wherein the spare memory row has a memory failure pattern, and reading data from the spare memory row.

First claim

The invention claimed is:

1. A method comprising:
mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device,
wherein the spare memory row has a memory failure pattern reading data from the spare memory row; and
generating a write request to an address associated with the spare memory row having the memory failure pattern before reading the data from the spare memory row.

2. The method of claim 1 ,
changing at least one bit of the memory failure pattern.

3. The method of claim 1 ,
determining a response of a memory controller to the memory failure pattern; and
comparing the response of the memory controller to a predetermined response to the memory failure pattern.

4. The method of claim 1 , further comprising:
mapping the spare memory row of the computing device to a second address of the computing device.

5. The method of claim 1 wherein the memory includes a post-package repair register, wherein the post-package repair register is used to change the memory failure pattern.

6. A system comprising:
a memory comprising a spare row that further includes a failure pattern, a memory controller to:
read, using post-package repair remapping, data from the spare row of the memory having the failure pattern; and
determine whether the failure pattern is correctable or uncorrectable.

7. The system of claim 6 , further comprising at least one processor,
wherein responsive to determining the failure pattern is correctable, the at least one processor is further to determine whether the memory controller corrected an error associated with the correctable failure pattern.

8. The system of claim 6 , wherein the memory controller is to:
use at least one of hard post-package repair or soft post-package repair responsive to determining that the failure pattern is uncorrectable.

9. The system of claim 6 , further comprising at least one processor to:
generate a write request at a particular memory address associated with the spare row; and
responsive to generating the write request, generate at least one read request at the address associated with the spare row.

10. The system of claim 6 , wherein the memory includes a post-package repair register, wherein the post-package repair register is used to change the failure pattern.

11. The system of claim 6 , wherein the failure pattern comprises at least one of: a stuck-at one bit, or a stuck-at zero bit.

12. The system of claim 6 , wherein the memory comprises a synchronous dynamic random access memory (SDRAM) module.

13. A non-transitory machine-readable storage medium including instructions stored thereon that, when executed, cause at least one processor to:
issue a post-package repair request to a memory controller to remap a row of a memory to a spare row of the memory, wherein the request disassociates the row from an address and associates the spare row with the address;
write a failure pattern to a spare row of a memory using a post-package repair capability of the memory;
issue a read request to the memory controller for the address associated with the spare row;
determine whether the failure pattern is correctable or uncorrectable.

14. The non-transitory machine-readable storage medium of claim 13 , wherein the instructions that cause the at least one processor to issue a post-package repair request to the memory controller further cause the memory controller to issue a post-package repair request to a post-package repair control register of the memory.

15. The non-transitory machine-readable storage medium of claim 13 , wherein the instructions cause the at least one processor to determine whether the memory controller corrected an error associated with the correctable failure pattern responsive to determining the failure pattern is correctable, the at least one processor is further.

16. The non-transitory machine-readable storage medium of claim 13 , wherein the instructions cause the at least one processor to use at least one of hard post-package repair or soft post-package repair responsive to determining that the failure pattern is uncorrectable.

17. The non-transitory machine-readable storage medium of claim 13 , wherein the instructions cause the at least one processor to:
generate a write request at a particular memory address associated with the spare row; and
responsive to generating the write request, generate at least one read request at the address associated with the spare row.

18. The non-transitory machine-readable storage medium of claim 13 , wherein the memory includes a post-package repair register, and the post-package repair register is used to change the failure pattern.

19. The non-transitory machine-readable storage medium of claim 13 , wherein the failure pattern comprises at least one of: a stuck-at one bit, or a stuck-at zero bit.

20. The non-transitory machine-readable storage medium of claim 13 , wherein the memory comprises a synchronous dynamic random access memory (SDRAM) module.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Pope Eric L
• Faasse Scott P

Classifications

• G11C29/10

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G11C29/76 Primary

  using address translation or modifications · CPC title