Memory device performing post package repair (PPR) operation

Patent metadata

Field	Value
Publication number	US-9870293-B2
Application number	US-201615345592-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Dec 24, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines, and control logic configured to control execution of a post package repair operation by the memory device. The control logic includes a PPR control circuit that programs a bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.

First claim

What is claimed is:

1. A memory device that receives from a memory controller a bad row address designating a bad row associated with a bad word line and one of a normal post package repair (PPR) command and a fast PPR (sPPR) command, the memory device comprising:
a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines; and
a control logic configured to control execution of a PPR operation by the memory device,
wherein the control logic comprises a PPR control circuit that programs the bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.

2. The memory device of claim 1 , wherein the replacing of the bad row in the memory cell array with the redundancy row comprises copying data from memory cells connected to the bad row to redundancy memory cells connected to the redundancy row.

3. The memory device of claim 2 , further comprising an address buffer that receives the bad row address from the memory controller and provides the bad row address to the control logic.

4. The memory device of claim 3 , wherein the control logic further comprises:
a command decoder that decodes the one of the normal PPR command and fast PPR command received from the memory controller; and
a mode register responsive to an output of the command decoder that sets a PPR mode for the memory device by generating a mode set signal.

5. The memory device of claim 4 , wherein the PPR control circuit selects a repair control signal from among a plurality of repair control signals in response to the mode set signal and provides the selected repair control signal to the memory cell array.

6. The memory device of claim 5 , wherein the memory cell array executes the normal PPR operation in response to one of the plurality of repair control signals and executes the fast PPR operation in response to another one of the plurality of repair control signals.

7. The memory device of claim 2 , wherein the normal PPR operation is executed during a first program time and the fast PPR operation is executed during a second program time shorter than the first program time.

8. The memory device of claim 2 , wherein the PPR control circuit comprises:
a bad address storage that stores the bad row address; and
a sensing and latching unit that reads the bad row address from the bad address storage and generates a repair control signal provided to the memory cell array that causes the replacing of the bad row in the memory cell array with the redundancy row.

9. The memory device of claim 2 , wherein memory cells of the memory cell array are arranged according to a first bank and a second bank, and the normal PPR operation is an internal bank copy operation wherein the bad word line and the redundancy word line are each disposed in the first bank.

10. The memory device of claim 2 , wherein memory cells of the memory cell array are arranged according to a first bank and a second bank, and the normal PPR operation is an inter bank copy operation wherein the bad word line is disposed in the first bank and the redundancy word line is disposed in the second bank.

11. The memory device of claim 1 , wherein the replacing of the bad row in the memory cell array with the redundancy row comprises writing a known data pattern to the redundancy memory cells connected to the redundancy row.

12. A memory device that receives from a memory controller a bad column address designating a bad column associated with a bad bit line and one of a normal post package repair (PPR) command and a fast PPR (sPPR) command, the memory device comprising:
a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy bit line and the word lines; and
a control logic configured to control execution of a PPR operation by the memory device,
wherein the control logic comprises a PPR control circuit that programs the bad column address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad column address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad column in the memory cell array with a redundancy column associated with the redundancy bit line.

13. The memory device of claim 12 , wherein the replacing of the bad column in the memory cell array comprises copying data from memory cells connected to the bad column to redundancy memory cells connected to the redundancy column.

14. The memory device of claim 13 , further comprising an address buffer that receives the bad row address from the memory controller and provides the bad row address to the control logic, wherein the control logic further comprises a command decoder that decodes the one of the normal PPR command and fast PPR command received from the memory controller, and a mode register responsive to an output of the command decoder that sets a PPR mode for the memory device by generating a mode set signal.

15. The memory device of claim 14 , wherein the PPR control circuit selects a repair control signal from among a plurality of repair control signals in response to the mode set signal and provides the selected repair control signal to the memory cell array.

16. The memory device of claim 15 , wherein the memory cell array executes the normal PPR operation in response to one of the plurality of repair control signals and executes the fast PPR operation in response to another one of the plurality of repair control signals.

17. The memory device of claim 13 , wherein the normal PPR operation is executed during a first program time and the fast PPR operation is executed during a second program time shorter than the first program time.

18. The memory device of claim 13 , wherein the replacing of the bad column in the memory cell array with the redundancy column comprises writing a known data pattern to the redundancy memory cells connected to the redundancy row.

19. A method of operating a memory device which includes memory cells connected to word lines and bit lines, and redundancy memory cells connected to one of a redundancy bit line and a redundancy word line, the method comprising:
entering a one of a normal post package repair (PPR) mode or a fast PPR mode in response to a received PPR command and a bad address, the bad address being one of: a bad column address designating a bad column and a bad row address designating a bad row;
when in the normal PPR mode, storing the bad address to a non-volatile memory;
when in the fast PPR mode, storing the bad address to a volatile memory;
when the bad address is the bad column address, replacing the bad column in the memory cell array with a redundancy column associated with the redundancy bit line;
when the bad address is the bad row address, replacing the bad row in the memory cell array with a redundancy row associated with the redundancy word line; and
writing data to the redundancy memory cells replacing memory cells selected by the bad address.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Seong-Jin
• Jung Ju-Yun
• Lee Yoo-Jung

Classifications

• G11C29/84 Primary

  with improved access time or stability · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G06F2201/805

  Real-time · CPC title

• G06F11/2094 Primary

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title