Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-12475361-B2
Application number	US-202017611207-A
Country	US
Kind code	B2
Filing date	May 7, 2020
Priority date	May 17, 2019
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

First claim

The invention claimed is:

1 . A semiconductor device comprising a cell and a first circuit,
wherein the first circuit comprises a first capacitor, a first input terminal, a second input terminal, and a second circuit, wherein the cell is electrically connected to the first input terminal through a first wiring, wherein the cell is electrically connected to the second input terminal through a second wiring, wherein the cell is configured to:
hold first data; and
pass a first current corresponding to the first data and second data between the cell and the first wiring and pass a second current corresponding to the first data and the second data between the cell and the second wiring when the second data is input to the cell,
wherein the first capacitor is configured to hold a differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current, and wherein the second circuit is configured to obtain the differential voltage and output a signal corresponding to the differential voltage.

2 . The semiconductor device according to claim 1 ,
wherein the first circuit comprises a first current-voltage converter circuit, a second current-voltage converter circuit, a first switch, a second switch, a third switch, and a fourth switch, wherein the first input terminal is electrically connected to a first terminal of the first switch and a first terminal of the first current-voltage converter circuit, wherein a second terminal of the first switch is electrically connected to a first terminal of the second switch and a first terminal of the first capacitor, wherein the second input terminal is electrically connected to a first terminal of the third switch and a first terminal of the second current-voltage converter circuit, wherein a second terminal of the third switch is electrically connected to a first terminal of the fourth switch and a second terminal of the first capacitor, wherein a second terminal of the fourth switch is electrically connected to a first terminal of the second circuit, wherein the first current-voltage converter circuit is configured to set a potential of the first terminal of the first current-voltage converter circuit to the first potential on the basis of the first current input to the first terminal of the first current-voltage converter circuit, and wherein the second current-voltage converter circuit is configured to set a potential of the first terminal of the second current-voltage converter circuit to the second potential on the basis of the second current input to the first terminal of the second current-voltage converter circuit.

3 . The semiconductor device according to claim 2 ,
wherein a second terminal of the second switch is electrically connected to a third wiring supplying a reference potential, and wherein the first circuit is configured to:
set the first terminal of the first capacitor to the first potential and set the second terminal of the first capacitor to the second potential by turning on the first switch and the third switch and turning off the second switch and the fourth switch;
change the second potential of the second terminal of the first capacitor to a third potential owing to a capacitive coupling caused by a change of the potential of the first terminal of the first capacitor from the first potential to the reference potential by turning off the first switch, the third switch, and the fourth switch and turning on the second switch; and
input the third potential corresponding to the differential voltage to the first terminal of the second circuit by turning off the first switch, the second switch, and the third switch and turning on the fourth switch.

4 . A semiconductor device comprising a cell and a first circuit,
wherein the first circuit comprises a first capacitor, a second capacitor, a first input terminal, and a second input terminal, wherein the cell is electrically connected to the first input terminal through a first wiring, wherein the cell is electrically connected to the second input terminal through a second wiring, wherein the cell is configured to:
hold first data; and
pass a first current corresponding to the first data and second data between the cell and the first wiring and pass a second current corresponding to the first data and the second data between the cell and the second wiring when the second data is input to the cell,
wherein the first capacitor is configured to hold a first differential voltage between a first potential corresponding to the first current and a second potential corresponding to the second current, and wherein the second capacitor is configured to hold a second differential voltage between the first potential corresponding to the first current and the second potential corresponding to the second current.

5 . The semiconductor device according to claim 4 ,
wherein the first circuit comprises a second circuit and a third circuit, wherein the second circuit is configured to obtain the first differential voltage based on a potential of a first terminal of the first capacitor and output a first signal corresponding to the first differential voltage, and wherein the third circuit is configured to obtain the second differential voltage based on a potential of a second terminal of the second capacitor and output a second signal corresponding to the second differential voltage.

6 . The semiconductor device according to claim 5 ,
wherein the first circuit comprises a first current-voltage converter circuit, a second current-voltage converter circuit, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch, wherein the first input terminal is electrically connected to a first terminal of the first switch, a first terminal of the fifth switch, and a first terminal of the first current-voltage converter circuit, wherein a second terminal of the first switch is electrically connected to a first terminal of the second switch and the first terminal of the first capacitor, wherein a second terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a first terminal of the second capacitor, wherein the second input terminal is electrically connected to a first terminal of the third switch, a first terminal of the seventh switch, and a first terminal of the second current-voltage converter circuit, wherein a second terminal of the third switch is electrically connected to a first terminal of the fourth switch and a second terminal of the first capacitor, wherein a second terminal of the seventh switch is electrically connected to a first terminal of the eighth switch and the second terminal of the second capacitor, wherein a second terminal of the fourth switch is electrically connected to a first terminal of the second circuit, wherein a second terminal of the sixth switch is electrically connected to a first terminal of the third circuit, wherein the first current-voltage converter circuit is configured to set a potential of the first terminal of the first current-voltage converter circuit to the first potential on the basis of the first current input to the first terminal of the first current-voltage converter circuit, and wherein the second current-voltage converter circuit is configured to set a potential of the first terminal of the second current-voltage converter circuit to the second potential on the basis of the second current input to the first terminal of the second current-voltage converter circuit.

7 . The semiconductor device according to claim 6 ,
wherein a second terminal of the second switch is electrically connected to a third

Assignees

• Semiconductor Energy Lab

Inventors

• Kimura Hajime
• Kozuma Munehiro

Classifications

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• G06G7/60

  for living beings, e.g. their nervous systems {; for problems in the medical field} · CPC title

• G06G7/19

  for forming integrals of products, e.g. Fourier integrals, Laplace integrals or correlation integrals; for analysis or synthesis of functions using orthogonal functions · CPC title