Semiconductor device

Patent metadata

Field	Value
Publication number	US-2017263291-A1
Application number	US-201715443015-A
Country	US
Kind code	A1
Filing date	Feb 27, 2017
Priority date	Mar 10, 2016
Publication date	Sep 14, 2017
Grant date	—

Abstract

The circuit scale of a semiconductor device that can perform arithmetic processing of analog data is reduced. In the semiconductor device, a memory cell is configured to generate a first current corresponding to first analog data and to generate a second current corresponding to the first analog data and second analog data. A reference memory cell is configured to generate a reference current corresponding to reference data. A first circuit is configured to generate and hold a third current corresponding to the difference between the first current and the reference current when the first current is lower than the reference current. A second circuit is configured to generate and hold a fourth current corresponding to the difference between the first current and the reference current when the first current is higher than the reference current. One of the first circuit and the second circuit is configured to generate a fifth current corresponding to third analog data.

First claim

1 . A semiconductor device comprising:
a memory cell, a reference memory cell, a first circuit, and a second circuit, wherein the memory cell is configured to generate a first current corresponding to first analog data and to generate a second current corresponding to the first analog data and second analog data, wherein the reference memory cell is configured to generate a reference current corresponding to reference data, wherein the first circuit is configured to generate and hold a third current corresponding to a difference between the first current and the reference current when the first current is lower than the reference current, wherein the second circuit is configured to generate and hold a fourth current corresponding to a difference between the first current and the reference current when the first current is higher than the reference current, and wherein one of the first circuit and the second circuit is configured to generate a fifth current corresponding to third analog data from the second current and one of the third current and the fourth current.

2 . The semiconductor device according to claim 1 , further comprising:
a first wiring electrically connected to the first circuit, the second circuit, and the memory cell; and a second wiring electrically connected to the reference memory cell.

3 . The semiconductor device according to claim 1 , further comprising:
a current source circuit; a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, and the memory cell; and a second wiring electrically connected to the current source circuit and the reference memory cell.

4 . The semiconductor device according to claim 1 ,
wherein each of the memory cell and the reference memory cell comprises a transistor, and wherein the semiconductor device further comprises:
a current source circuit;
a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, and one of a source and a drain of the transistor of the memory cell; and
a second wiring electrically connected to the current source circuit and one of a source and a drain of the transistor of the reference memory cell.

5 . The semiconductor device according to claim 1 ,
wherein each of the memory cell and the reference memory cell comprises a first transistor, a second transistor, and a capacitor, wherein the semiconductor device further comprises:
a current source circuit;
a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, and one of a source and a drain of the first transistor of the memory cell; and
a second wiring electrically connected to the current source circuit and one of a source and a drain of the first transistor of the reference memory cell, and
wherein in each of the memory cell and the reference memory cell, a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and an electrode of the capacitor.

6 . The semiconductor device according to claim 1 , further comprising a switch between the first circuit and the second circuit.

7 . The semiconductor device according to claim 1 , wherein the semiconductor device is configured to perform a product-sum operation.

8 . A semiconductor device comprising:
a first memory cell, a second memory cell, a first reference memory cell, a second reference memory cell, a first circuit, and a second circuit, wherein the first memory cell is configured to generate a first current corresponding to a first analog potential and to generate a second current corresponding to the first analog potential and a second analog potential, wherein the second memory cell is configured to generate a third current corresponding to a third analog potential and to generate a fourth current corresponding to the third analog potential and a fourth analog potential, wherein the first reference memory cell is configured to generate a first reference current corresponding to a reference potential, wherein the second reference memory cell is configured to generate a second reference current corresponding to the reference potential, wherein the first circuit is configured to generate and hold a fifth current corresponding to a difference between a sum of the first current and the third current and a sum of the first reference current and the second reference current when the sum of the first current and the third current is smaller than the sum of the first reference current and the second reference current, wherein the second circuit is configured to generate and hold a sixth current corresponding to a difference between the sum of the first current and the third current and the sum of the first reference current and the second reference current when the sum of the first current and the third current is larger than the sum of the first reference current and the second reference current, and wherein one of the first circuit and the second circuit is configured to generate a seventh current corresponding to a fifth analog potential from a sum of the second current and the fourth current and one of the fifth current and the sixth current.

9 . The semiconductor device according to claim 8 , further comprising:
a first wiring electrically connected to the first circuit, the second circuit, the first memory cell, and the second memory cell; and a second wiring electrically connected to the first reference memory cell and the second reference memory cell.

10 . The semiconductor device according to claim 8 , further comprising:
a current source circuit; a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, the first memory cell, and the second memory cell; and a second wiring electrically connected to the current source circuit, the first reference memory cell, and the second reference memory cell.

11 . The semiconductor device according to claim 8 ,
wherein each of the first memory cell, the second memory cell, the first reference memory cell, and the second reference memory cell comprises a transistor, and wherein the semiconductor device further comprises:
a current source circuit;
a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, and one of a source and a drain of the transistor of each of the first memory cell and the second memory cell; and
a second wiring electrically connected to the current source circuit and one of a source and a drain of the transistor of each of the first reference memory cell and the second reference memory cell.

12 . The semiconductor device according to claim 8 ,
wherein each of the first memory cell, the second memory cell, the first reference memory cell, and the second reference memory cell comprises a first transistor, a second transistor, and a capacitor, wherein the semiconductor device further comprises:
a current source circuit;
a first wiring electrically connected to the current source circuit, the first circuit, the second circuit, and one of a source and a drain of the first transistor of each of the first memory cell and the second memory cell; and
a second wiring electrically connected to the current source circuit and one of a source and a drain of the first transistor of each of the first reference memory cell and the second reference memory cell, and
wherein in each of the first memory cell, the second memory cell, the first reference memory cell, and the second reference memory cell, a gate of the first transistor is electrically connected to one of a source and a

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G06F2207/4814

  Non-logic devices, e.g. operational amplifiers · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/00 Primary

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title

• G06F17/00

  Digital computing or data processing equipment or methods, specially adapted for specific functions (information retrieval, database structures or file system structures therefor G06F16/00) · CPC title