Resist patterned redistribution wiring on copper polyimide via layer

Patent metadata

Field	Value
Publication number	US-12469787-B2
Application number	US-202217651883-A
Country	US
Kind code	B2
Filing date	Feb 21, 2022
Priority date	Feb 21, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

First claim

What is claimed is:

1 . A semiconductor element, comprising:
a conductive pad; a first layer of a first polyimide material having an uppermost surface, the first layer including a via trench extending through the first layer from the uppermost surface to the conductive pad; a second layer of a second polyimide material arranged in direct contact with the uppermost surface, the second layer including a line trench extending to the uppermost surface; and a conductive structure arranged in the via trench and the line trench, wherein a sidewall of a line of the conductive structure arranged in the line trench includes a cap that is in direct contact with the second polyimide material.

2 . The semiconductor element of claim 1 , wherein the conductive structure includes copper that extends continuously and uninterruptedly from the via trench to the line trench.

3 . The semiconductor element of claim 1 , wherein the first polyimide material is a photosensitive polyimide material.

4 . The semiconductor element of claim 1 , wherein the second polyimide material is a non-photosensitive polyimide material.

5 . The semiconductor element of claim 1 , further comprising:
a further conductive pad; and a further via trench in the first layer extending through the first layer from the uppermost surface to the further conductive pad, wherein: the conductive structure is also arranged in the further via trench.

6 . The semiconductor element of claim 1 , wherein:
the sidewall is substantially planar.

7 . The semiconductor element of claim 6 , wherein the sidewall is substantially orthogonal to the uppermost surface.

8 . A method of making a semiconductor element, the method comprising:
forming a via trench in a polyimide layer such that the via trench extends through the polyimide layer from an uppermost surface of the polyimide layer to a conductive pad arranged beneath the polyimide layer; forming a resist layer above the uppermost surface of the polyimide layer; patterning the resist layer to form a resist trench defined by resist sidewalls; metallizing the via trench to form a via and the resist trench to form a line having line sidewalls in direct contact with the resist sidewalls; removing the patterned resist layer such that the line sidewalls are exposed; forming a cap to cover the exposed line sidewalls; and forming a further polyimide layer in direct contact with the cap.

9 . The method of claim 8 , wherein the via trench and the resist trench are metallized without performing any intervening operations.

10 . The method of claim 8 , wherein forming the resist layer includes spin applying the resist.

11 . The method of claim 8 , further comprising:
prior to forming the via trench: forming the conductive pad in a base layer of polyimide material; planarizing the base layer to an uppermost surface of the conductive pad such that the base layer and the conductive pad form a planarized surface; and forming the polyimide layer on the planarized surface.

12 . The method of claim 8 , wherein patterning the resist layer includes forming the resist trench such that the resist sidewalls are substantially orthogonal to the uppermost surface of the polyimide layer.

13 . The method of claim 8 , further comprising:
depositing a seed layer on the polyimide layer prior to forming the resist layer.

14 . The method of claim 8 , further comprising:
planarizing the further polyimide layer to an uppermost surface of the line such that the further polyimide layer and the line form a planarized surface.

15 . The method of claim 14 , further comprising:
forming a second polyimide layer on the planarized surface; forming a second via trench in the second polyimide layer such that second via trench extends through the second polyimide layer from an uppermost surface of the second polyimide layer to the uppermost surface of the line; forming a second resist layer above the uppermost surface of the second polyimide layer; patterning the second resist layer to form a second resist trench defined by second resist sidewalls; metallizing the second via trench to form a second via and the second resist trench to form a second line having second line sidewalls in direct contact with the second resist sidewalls; removing the patterned second resist layer such that the second line sidewalls are exposed; and forming a second further polyimide layer in direct contact with the exposed second line sidewalls.

16 . The method of claim 15 , wherein the second via trench and the second resist trench are metallized without performing any intervening operations.

17 . A method of making a semiconductor element, the method comprising:
forming a resist layer above a polyimide layer; patterning the resist layer to form a resist trench defined by resist sidewalls such that the resist trench extends through the resist layer to a via trench formed in the polyimide layer; metallizing the via trench and the resist trench to form a continuous conductive structure arranged in the via trench and in the resist trench such that the conductive structure forms a line having line sidewalls in direct contact with the resist sidewalls; removing the patterned resist layer such that the line sidewalls are exposed; forming a cap to cover the exposed line sidewalls; and forming a further polyimide layer in direct contact with the cap.

18 . The method of claim 17 , wherein the via trench and the resist trench are metallized without performing any intervening operations.

19 . The method of claim 17 , further comprising:
prior to forming the resist layer: forming a conductive pad in a base layer of polyimide material; planarizing the base layer to an uppermost surface of the conductive pad such that the base layer and the conductive pad form a planarized surface; and forming the polyimide layer on the planarized surface.

Assignees

• IBM

Inventors

• Farooq Mukta Ghate
• Kelly James J
• Perfecto Eric
• Skordas Spyridon
• Mcherron Dale Curtis

Classifications

• H10P14/683

  carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/48 Primary

  Insulating materials thereof · CPC title

• H10W72/019 Primary

  of bond pads · CPC title