3D stacked-chip package

Patent metadata

Field	Value
Publication number	US-10373885-B2
Application number	US-201715608466-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	Apr 30, 2014
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.

First claim

What is claimed is:

1. A method, comprising:
bonding a first die to a second die by directly bonding a first oxide layer of the first die to a second oxide layer of the second die with an oxide-to-oxide bond, the first die comprises a first semiconductor substrate and the second die comprises a second semiconductor substrate;
forming a first opening in the second die after the bonding the first die to the second die, wherein the first opening extends through the second semiconductor substrate and exposes a first conductive element of the first die or the second die;
forming a first via in the first opening, the first via is electrically insulated from the second semiconductor substrate by a first spacer;
mounting a third die over the second die, the third die having a third semiconductor substrate;
forming a second opening in the third die after the mounting the third die over the second die, the second opening extending through the third semiconductor substrate and exposing the first via; and
forming a second via in the second opening, the second via is electrically insulated from the third semiconductor substrate by a second spacer.

2. The method of claim 1 , further comprising:
forming a first molding compound over the first die and around the second die prior to the forming the first via; and
forming a second molding compound around the third die prior to the forming the second via.

3. The method of claim 2 , wherein the first molding compound is disposed between the second die and the third die along a direction perpendicular to a major surface of the second semiconductor substrate.

4. The method of claim 2 , further comprising:
forming a third via extending through the first molding compound adjacent the second die prior to the mounting the third die, wherein the third via extends through the first molding compound and contacts a second conductive element of the first die.

5. The method of claim 4 , further comprising forming a fourth via through the second molding compound, wherein the fourth via contacts at least one of the first via or the third via.

6. The method of claim 1 , further comprising:
prior to forming the first via, depositing a spacer layer along sidewalls and a bottom surface of the first opening; and
etching the spacer layer to remove lateral portions of the spacer layer and define the first spacer.

7. The method of claim 1 , wherein the first conductive element is disposed in the first die, and wherein the first opening further exposes a third conductive element of the second die over the first conductive element.

8. The method of claim 1 , wherein the third conductive element acts as an etch stop layer during forming the first opening.

9. A method comprising:
bonding first semiconductor die to a second semiconductor die using a direct oxide-to-oxide bond;
forming an insulating material over a first one of the first semiconductor die and the second semiconductor die, the insulating material at least laterally encapsulating a second one of the first semiconductor die and the second semiconductor die;
patterning a first opening extending through a first semiconductor substrate of the first semiconductor die;
forming a first spacer along a first sidewall of the first opening; and
forming a conductive via in the first opening, the first spacer electrically insulates the conductive via from the first semiconductor substrate.

10. The method of claim 9 , wherein the insulating material comprises a molding compound.

11. The method of claim 9 , wherein a width of the first one of the first semiconductor die and the second semiconductor die has a different width than the second one of the first semiconductor die and the second semiconductor die.

12. The method of claim 9 , further comprising planarizing the insulating material so that a lateral surface of the insulating material is substantially level with a lateral surface of the second one of the first semiconductor die and the second semiconductor die.

13. The method of claim 9 , wherein forming the insulating material further comprises forming the insulating material over the second one of the first semiconductor die and the second semiconductor die, and wherein patterning the first opening further comprises patterning the first opening through at least a portion of the insulating material.

14. The method of claim 9 , further comprising forming redistribution layers over the first semiconductor die and the second semiconductor die, wherein the redistribution layers are electrically connected to the conductive via.

15. The method of claim 9 , wherein patterning the first opening comprises exposing a first conductive feature in the second semiconductor die.

16. The method of claim 9 , wherein patterning the first opening further comprises exposing a second conductive feature in the first semiconductor die.

17. A method comprising:
bonding first semiconductor die to a second semiconductor die, the first semiconductor die comprising a first semiconductor substrate, and the second semiconductor die comprising a second semiconductor substrate;
forming a first insulating material over the first semiconductor die and around the second semiconductor die;
patterning a first opening extending through the second semiconductor substrate and a portion of the first insulating material above the second semiconductor substrate;
forming a first spacer along a first sidewall of the first opening; and
forming a first conductive via in the first opening, the first spacer electrically insulates the first conductive via from the second semiconductor substrate.

18. The method of claim 17 , wherein a first portion of the first conductive via in the portion of the first insulating material above the second semiconductor substrate is wider than a second portion of the first conductive via in the second semiconductor substrate.

19. The method of claim 17 further comprising:
disposing a third semiconductor die over the second semiconductor die, the third semiconductor die comprising a third semiconductor substrate;
encapsulating the third semiconductor die in a second insulating material disposed over the first insulating material;
patterning a second opening extending through at least a portion of the second insulating material; and
forming a second conductive via in the second opening, the second conductive via contacting the first conductive via.

20. The method of claim 19 , wherein the second conductive via is laterally spaced apart from the second semiconductor die, and wherein the first conductive via has a fan-out configuration extending laterally past a sidewall of the second semiconductor die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Chen Ming-Fa
• Lu Wen-Sen
• Chiou Wen-Chih
• Tsai Wen-Ching

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title