Package structure including a die having a taper-shaped die connector

US12469757B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12469757-B2
Application numberUS-202418652779-A
CountryUS
Kind codeB2
Filing dateMay 1, 2024
Priority dateMay 28, 2020
Publication dateNov 11, 2025
Grant dateNov 11, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a package structure including a first die and an encapsulant. The first die includes a substrate, a plurality of pads over the substrate, a passivation layer on portions of each of the plurality of pads, a plurality of first die connectors on the plurality of pads, respectively and a dielectric layer laterally encapsulating the plurality of first die connectors. The encapsulant laterally encapsulates the first die. One of the plurality of first die connectors is a taper-shaped die connector. A width of the one of the plurality of first die connectors gradually increases from a top surface of the one of the plurality of first die connectors toward the a top surface of the passivation layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A package structure, comprising: a first die comprising: a substrate; a plurality of pads over the substrate; a passivation layer on portions of each of the plurality of pads; a plurality of first die connectors on the plurality of pads, respectively; and a dielectric layer laterally encapsulating the plurality of first die connectors; an encapsulant laterally encapsulating the first die, wherein one of the plurality of first die connectors is a taper-shaped die connector, and a width of the one of the plurality of first die connectors gradually increases from a top surface of the one of the plurality of first die connectors toward a top surface of the passivation layer. 2 . The package structure of claim 1 , wherein the first die further comprises a plurality of conductive caps respectively on the plurality of first die connectors. 3 . The package structure of claim 2 , wherein the first die comprises a memory die. 4 . The package structure of claim 2 , further comprising: an encapsulant laterally encapsulating the first die, wherein top surfaces of the plurality of conductive caps and a top surface of the encapsulant are substantially coplanar. 5 . The package structure of claim 4 , further comprising: a redistribution structure, disposed over the encapsulant and electrically connected with the plurality of first die connectors passing through the plurality of conductive caps of the first die. 6 . The package structure of claim 5 , wherein the first die further comprises: a dielectric layer laterally encapsulating the plurality of conductive caps and the plurality of first die connectors, wherein the redistribution structure is in contact with the encapsulant, the dielectric layer and the plurality of conductive caps. 7 . The package structure of claim 6 , wherein a bottom surface of the redistribution structure is lower than a top surface of the dielectric layer. 8 . The package structure of claim 5 , further comprising: a second die, laterally aside the first die, wherein the second die comprises a plurality of second die connectors, and the top surface of the one of the plurality of first die connectors is lower than a top surface of the plurality of second die connectors. 9 . The package structure of claim 8 , wherein the redistribution structure comprising: a plurality of first vias, respectively connected to the plurality of first die connectors; and a plurality of second vias, respectively connected to the plurality of second die connectors, wherein one of the plurality of first vias is deeper than one of the plurality of second vias. 10 . The package structure of claim 5 , further comprising: a plurality of through vias laterally encapsulated by the encapsulant, and connected to the redistribution structure, wherein sidewalls of the plurality of through vias are more vertical than sidewalls of the plurality of first die connectors. 11 . A package structure, comprising: at least one die comprising: a substrate; a plurality of pads over the substrate; a passivation layer on portions of each of the plurality of pads; a plurality of die connectors on the plurality of pads, respectively; and a dielectric layer on the passivation layer, an encapsulant laterally encapsulating the at least one die, wherein each of the plurality of die connectors is a taper-shaped die connector, and comprises: a bottom part located in the passivation layer; and a top part on the bottom part and located in the dielectric layer, and wherein a first dimension of a top side of the top part is less than a second dimension of a bottom side of the top part. 12 . The package structure of claim 11 , wherein a third dimension of a top side of the bottom part is larger than a fourth dimension of a bottom side of the bottom part, and the second dimension of the bottom side of the top part is larger than the third dimension of the top side of the bottom part. 13 . The package structure of claim 11 , wherein a bottom surface of the top part is in contact with a top surface of the passivation layer. 14 . The package structure of claim 11 , further comprising: a conductive cap located on a top surface of the top part. 15 . The package structure of claim 14 , wherein a fifth dimension of a bottom side of the conductive cap is less than the second dimension of the bottom side of the top part. 16 . The package structure of claim 14 , further comprising: a redistribution structure, disposed over the encapsulant and the at least one die, wherein redistribution structure comprises a via passing through the conductive cap and connected to the top part, and a top dimension of the via is greater than a bottom dimension of the via. 17 . A package structure, comprising: at least one die comprising a plurality of die connectors; a plurality of taper-shaped through vias, wherein one of the plurality of taper-shaped through vias comprises a conductive layer and a taper-shaped conductive pillar on the conductive layer; an encapsulant laterally encapsulating the at least one die, the conductive layer and the taper-shaped conductive pillar, wherein a width of the taper-shaped conductive pillar gradually increases along a first direction from a top surface of the taper-shaped conductive pillar toward the conductive layer, and one of the plurality of die connectors is a taper-shaped die connector. 18 . The package structure of claim 17 , wherein the taper-shaped die connector has a top part, and the top part has a width gradually increases along the first direction. 19 . The package structure of claim 18 , wherein the taper-shaped die connector has a bottom part, and the bottom part has a width gradually decreases along the first direction. 20 . The package structure of claim 19 , wherein a bottom width of the top part is larger than a top width of the bottom part.

Assignees

Inventors

Classifications

  • On different surfaces · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

  • Package configurations · CPC title

  • extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

  • Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

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What does patent US12469757B2 cover?
Provided is a package structure including a first die and an encapsulant. The first die includes a substrate, a plurality of pads over the substrate, a passivation layer on portions of each of the plurality of pads, a plurality of first die connectors on the plurality of pads, respectively and a dielectric layer laterally encapsulating the plurality of first die connectors. The encapsulant late…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/635. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 11 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).