Memory core circuits having cell-on-periphery structures and memory devices including the same

Patent metadata

Field	Value
Publication number	US-12469543-B2
Application number	US-202318325307-A
Country	US
Kind code	B2
Filing date	May 30, 2023
Priority date	Sep 21, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.

First claim

What is claimed is:

1 . A memory core circuit, comprising:
a memory cell array having a plurality of sub cell arrays therein, which are arranged in a matrix of sub cell array rows and sub cell array columns; and a core control circuit having a plurality of sub peripheral circuits therein, which are arranged such that each sub peripheral circuit extends underneath a corresponding sub cell array within the plurality of sub cell arrays; wherein each sub cell array includes a plurality of memory cells therein, which are connected to a plurality of wordlines and a plurality of bitlines; and wherein each sub peripheral circuit includes:
a plurality of sub wordline drivers, which are respectively configured to drive a corresponding wordline within the plurality of wordlines;
a plurality of bitline sense amplifiers, which are respectively configured to sense voltages on a corresponding bitline within the plurality of bitlines;
a row decoding circuit configured to control a corresponding plurality of sub wordline drivers and select one of the plurality of wordlines in response to an address of the selected one of the plurality of wordlines;
a power circuit configured to supply power within the sub peripheral circuit; and
a control circuit configured to control operation of the sub peripheral circuit.

2 . The memory core circuit of claim 1 , wherein each sub peripheral circuit is partitioned into:
a wordline driver region including the plurality of sub wordline drivers; a sense amplifier region including the plurality of bitline sense amplifiers; a decoder region including the row decoding circuit; and a power and control region including the power circuit and the control circuit.

3 . The memory core circuit of claim 2 , wherein the wordline driver region, the sense amplifier region, the decoder region and the power and control region are arranged in a row direction.

4 . The memory core circuit of claim 2 ,
wherein the wordline driver region and the sense amplifier region are disposed at both ends in a row direction of each sub peripheral circuit; wherein the decoder region extends adjacent to the wordline driver region in the row direction, and between the wordline driver region and the sense amplifier region; and wherein the power and control regions extend adjacent to the sense amplifier region in the row direction, and between the wordline driver region and the sense amplifier region.

5 . The memory core circuit of claim 2 , wherein an area of the sense amplifier region is about half an area of each sub peripheral circuit.

6 . The memory core circuit of claim 2 , wherein the core control circuit has a shift structure such that, with respect to a first sub peripheral circuit and a second sub peripheral circuit that are adjacent in a row direction, the wordline driver region of the first sub peripheral circuit extends adjacent, in the row direction, to the sense amplifier region of the second sub peripheral circuit.

7 . The memory core circuit of claim 6 , wherein each wordline is respectively connected to corresponding wordline driver regions of all of the sub peripheral circuits arranged into an equivalent row thereof.

8 . The memory core circuit of claim 6 , wherein, with respect to a third sub peripheral circuit and a fourth sub peripheral circuit that are adjacent to each other in a column direction, the sense amplifier region of the third sub peripheral circuit extends adjacent, in the column direction, to the wordline driver region of the fourth sub peripheral circuit.

9 . The memory core circuit of claim 2 , wherein the core control circuit has a mirror structure such that, with respect to a first sub peripheral circuit and a second sub peripheral circuit that are adjacent in a row direction, (i) the wordline driver region of the first sub peripheral circuit is adjacent, in the row direction, to the wordline driver region of the second sub peripheral circuit, or (ii) the sense amplifier region of the first sub peripheral circuit is adjacent, in the row direction, to the sense amplifier region of the second sub peripheral circuit.

10 . The memory core circuit of claim 9 ,
wherein a first wordline is connected to wordline driver regions of all of the odd-numbered sub peripheral circuits that are disposed in an equivalent row of sub peripheral circuits; and wherein a second wordline adjacent in a column direction to the first wordline is connected to wordline driver regions of all even-numbered sub peripheral circuits that are disposed in an equivalent row of sub peripheral circuits.

11 . The memory core circuit of claim 2 , wherein the sense amplifier region includes a plurality amplifier blocks arranged in a column direction, said plurality of amplifier blocks having the same number of bitline sense amplifiers therein.

12 . The memory core circuit of claim 11 , wherein the sense amplifier region further includes local sense amplifiers connecting local input-output lines and global input-output lines; and wherein the local sense amplifiers are disposed between two amplifier blocks that are adjacent to each other in the column direction.

13 . The memory core circuit of claim 2 , wherein the core control circuit further includes:
a plurality of dummy sub peripheral circuits that are disposed at both ends of the core control circuit in a row direction, each dummy sub peripheral circuit includes wordline driver region, the decoder region and the power and control region.

14 . The memory core circuit of claim 13 , wherein the core control circuit further includes voltage drivers that extend in edge regions, such that each edge region is between two dummy sub peripheral circuits that are adjacent to each other in a column direction.

15 . The memory core circuit of claim 2 , wherein each wordline is connected to the sub wordline driver included in the wordline driver region, using a vertical contact that is disposed in a boundary region between two sub peripheral circuits, which extend adjacent to each other in a row direction.

16 . The memory core circuit of claim 1 , wherein each memory cell includes a vertical channel transistor, and a cell capacitor extending above the vertical channel transistor.

17 . A memory core circuit, comprising:
a memory cell array having a plurality of sub cell arrays therein, which are arranged into a matrix of sub cell array rows and sub cell array columns; and a core control circuit having a plurality of sub peripheral circuits therein, which are arranged with each sub peripheral circuit extending underneath each corresponding sub cell array within the plurality of sub cell arrays; wherein each sub cell array includes a plurality of memory cells respectively connected to a plurality of wordlines and a plurality of bitlines; and wherein each sub peripheral circuit includes:
a wordline driver region including a plurality of sub wordline drivers;
a sense amplifier region including a plurality of bitline sense amplifiers;
a decoder region including a row decoding circuit; and
a power and control region including a power circuit and a control circuit.

18 . The memory core circuit of claim 17 ,
wherein the wordline driver region and the sense amplifier region are disposed at both ends in a row direction of each sub peripheral circuit; wherein the decoder region extends adjacent to the wordline driver region, in the row direction, and between the wordline driver region and the sense amplifier region; and wherein the power and control region extends adjacent, in the ro

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hoseok
• Seo Younghun
• Jeong Kangsub
• Kim Sangyun
• Lee Dongil

Classifications

• G11C11/4085 Primary

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title