Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue

Patent metadata

Field	Value
Publication number	US-11567700-B2
Application number	US-202117223684-A
Country	US
Kind code	B2
Filing date	Apr 6, 2021
Priority date	Feb 20, 2019
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

First claim

The invention claimed is:

1. A system comprising:
a plurality of memory components; and
a processing device operatively coupled with the plurality of memory components, the processing device configured to perform operations comprising:
scheduling a plurality of commands in a command queue, wherein scheduling the commands comprises, for each of the plurality of commands:
determining an age of a command based on an entrance time of the command in the command queue,
based on the age of the command satisfying a threshold, performing at least one of:
marking other commands in the command queue as not issuable when the command is a deterministic command, and
marking other commands in the command queue as not issuable when the command is a non-deterministic command and an intermediate command queue is not empty.

2. The system of claim 1 , wherein scheduling the commands further comprises, for each of the plurality of commands:
marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

3. The system of claim 2 , wherein the plurality of commands are directed to the plurality of memory components, and wherein the memory components comprises a volatile memory component receiving deterministic commands and a non-volatile memory component receiving non-deterministic commands, and
wherein the plurality of commands in the command queue comprise non-deterministic commands and deterministic commands.

4. The system of claim 3 , wherein the volatile memory component is a Dynamic Random-Access Memory (DRAM) and the non-volatile memory component is a Non-Volatile Dual In-Line Memory Module (NVDIMM), wherein the non-deterministic commands are NVDIMM-P commands, and deterministic commands are DRAM commands.

5. The system of claim 4 , wherein the intermediate command queue receives an intermediate command indicating that data associated with the non-deterministic read command is ready for transmission, wherein the non-deterministic read command is an XREAD command.

6. The system of claim 1 , wherein the processing device is configured to perform operations further comprising:
performing order buffer arbitration comprising:
receiving the non-deterministic command at a first port of an order buffer arbiter; and
adapting a maximum number of order buffer entries associated with the first port based on the deterministic command being at a second port of the order buffer arbiter.

7. The system of claim 6 , wherein the maximum number of order buffer entries associated with the first port is decreased to a predetermined contention limit associated with the first port when there is the deterministic command at the second port.

8. The system of claim 7 , wherein deterministic commands are received at the second port of the order buffer arbiter.

9. The system of claim 8 , wherein the maximum number of order buffer entries associated with the first port is set to a predetermined maximum limit associated with the first port when there is not the deterministic command at the second port.

10. The system of claim 9 , the processing device configured to perform operations further comprising:
pre-decoding the deterministic commands and the non-deterministic commands from the order buffer arbiter, wherein the plurality of commands received in the command queue comprise the pre-decoded commands.

11. A method comprising:
scheduling a plurality of commands in a command queue, wherein scheduling the commands comprises, for each of the plurality of commands:
determining an age of a command based on an entrance time of the command in the command queue,
based on the age of the command satisfying a threshold, performing at least one of:
marking other commands in the command queue as not issuable in response to the command being a deterministic command, and
marking other commands in the command queue as not issuable when the command is a non-deterministic command and an intermediate command queue is not empty.

12. The method of claim 11 , wherein scheduling the commands further comprises, for each of the plurality of commands:
marking the command as not issuable in response to the command being a non-deterministic read command and the intermediate command queue being empty.

13. The method of claim 12 , wherein the plurality of commands are directed to a plurality of memory components, and wherein the plurality of commands in the command queue comprise non-deterministic commands and deterministic commands, wherein the deterministic commands are commands to volatile memory components and the non-deterministic commands are commands to non-volatile memory components.

14. The method of claim 13 , wherein the volatile memory component is a Dynamic Random-Access Memory (DRAM) and the non-volatile memory component is a Non-Volatile Dual In-Line Memory Module (NVDIMM), wherein the non-deterministic commands are NVDIMM-P commands, and deterministic commands are DRAM commands.

15. The method of claim 14 , wherein the intermediate command queue receives an intermediate command indicating that data associated with the non-deterministic read command is ready for transmission, wherein the non-deterministic read command is an XREAD command.

16. The method of claim 11 , further comprising:
performing order buffer arbitration comprising:
receiving the non-deterministic command at a first port of an order buffer arbiter, and
adapting a maximum number of order buffer entries associated with the first port based on the deterministic command being at a second port of the order buffer arbiter.

17. The method of claim 16 , the maximum number of order buffer entries associated with the first port is decreased to a predetermined contention limit associated with the first port in response to the deterministic command being at the second port.

18. The method of claim 17 , wherein the maximum number of order buffer entries associated with the first port is set to a predetermined maximum limit associated with the first port in response to the deterministic command not being at the second port.

19. The method of claim 18 , further comprising:
pre-decoding the deterministic commands and the non-deterministic commands from the order buffer arbiter, wherein the plurality of commands received in the command queue comprise the pre-decoded commands.

20. At least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
scheduling a plurality of commands in a command queue, wherein scheduling the commands comprises, for each of the plurality of commands:
determining an age of a command based on an entrance time of the command in the command queue,
based on the age of the command satisfying a threshold, performing at least one of:
marking other commands in the command queue as not issuable when the command is a deterministic command, and
marking other commands in the command queue as not issuable when the command is a non-deterministic command and an intermediate command queue is not empty.

Assignees

• Micron Technology Inc

Inventors

• La Fratta Patrick A
• Walker Robert

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/1642

  with request queuing · CPC title