Host request pacing to balance resources and throughput

Patent metadata

Field	Value
Publication number	US-11922228-B2
Application number	US-202117350389-A
Country	US
Kind code	B2
Filing date	Jun 17, 2021
Priority date	Jun 17, 2021
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

Methods, computer program products, and/or systems are provided that perform the following operations: determining a pacing requirement for host requests based on one or more thresholds; setting a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement; and implementing a memory request flow for a host request based on the pacing requirement and the pacing delay level.

First claim

What is claimed is:

1. A computer-implemented method comprising:
determining a pacing requirement for host requests based on one or more thresholds;
setting a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement;
implementing a memory request flow for a host request based on the pacing requirement and the pacing delay level; and
processing the host request based on the implemented memory request flow.

2. The computer-implemented method of claim 1 , wherein setting the pacing delay level comprises setting a pace count indicative of a number of clock cycles to delay the host request, and wherein the pace count is decremented every clock cycle when the pace count is greater than zero.

3. The computer-implemented method of claim 1 , wherein the host requests include a write request and wherein the pacing requirement is determined based on available resources.

4. The computer-implemented method of claim 3 , wherein the one or more thresholds represent a level of available resources.

5. The computer-implemented method of claim 4 , wherein the pacing delay level is increased as the level of available resources decreases.

6. The computer-implemented method of claim 3 , wherein new host requests are added to a first in, first out queue in response to the pacing delay level being greater than zero.

7. The computer-implemented method of claim 3 , wherein new read requests are delayed until previously delayed write requests are processed.

8. The computer-implemented method of claim 1 , wherein the host requests include a read request and wherein the pacing requirement is based on exceeding a threshold long access time for an active read request.

9. The computer-implemented method of claim 8 , further comprising, in response to determining the active read request has exceeded the threshold long access time:
sending a pending read response that has not exceeded a pacing bypass threshold to a first in, first out queue; and
setting the pacing delay level to a defined number of clock cycles when the first in, first out queue includes one or more pending read responses,
wherein the memory request flow for the host request includes processing an oldest read response from the first in, first out queue based on the pacing delay level.

10. A computer program product comprising a computer-readable storage medium having stored thereon:
program instructions programmed to determine a pacing requirement for host requests based on one or more thresholds;
program instructions programmed to set a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement;
program instructions programmed to implement a memory request flow for a host request based on the pacing requirement and the pacing delay level; and
program instructions programmed to process the host request based on the implemented memory request flow.

11. The computer program product of claim 10 , wherein setting the pacing delay level comprises setting a pace count indicative of a number of clock cycles to delay the host request, and wherein the pace count is decremented every clock cycle when the pace count is greater than zero.

12. The computer program product of claim 10 , wherein the host requests include a write request and wherein the pacing requirement is determined based on available resources.

13. The computer program product of claim 12 , wherein the one or more thresholds represent a level of available resources and wherein the pacing delay level is increased as the level of available resources decreases.

14. The computer program product of claim 12 , wherein new host requests are added to a first in, first out queue in response to the pacing delay level being greater than zero.

15. The computer program product of claim 10 , wherein the host requests include a read request and wherein the pacing requirement is based on exceeding a threshold long access time for an active read request.

16. The computer program product of claim 15 , the computer-readable storage medium having further stored thereon:
program instructions programmed to, in response to determining the active read request has exceeded the threshold long access time, send a pending read response that has not exceeded a pacing bypass threshold to a first in, first out queue; and
program instructions programmed to set the pacing delay level to a defined number of clock cycles when the first in, first out queue includes one or more pending read responses;
wherein the memory request flow for the host request includes processing an oldest read response from the first in, first out queue based on the pacing delay level.

17. A computer system comprising:
a processor set; and
a computer-readable storage medium;
wherein:
the processor set is structured, located, connected and programmed to run program instructions stored on the computer-readable storage medium; and
the stored program instructions include:
program instructions programmed to determine a pacing requirement for host requests based on one or more thresholds;
program instructions programmed to set a pacing delay level based on the one or more thresholds in response to the determination of the pacing requirement;
program instructions programmed to implement a memory request flow for a host request based on the pacing requirement and the pacing delay level; and
program instructions programmed to process the host request based on the implemented memory request flow.

18. The computer system of claim 17 , wherein the host requests include a write request and wherein the pacing requirement is determined based on available resources.

19. The computer system of claim 17 , wherein new host requests are added to a first in, first out queue in response to the pacing delay level being greater than zero.

20. The computer system of claim 17 , wherein the host requests include a read request and wherein the pacing requirement is based on exceeding a threshold long access time for an active read request.

Assignees

• IBM

Inventors

• Weckwerth Rick A
• Moertl Daniel Frank
• Galbraith Robert Edward
• Szekely Matthew
• Jamsek Damir Anthony

Classifications

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F9/4887

  involving deadlines, e.g. rate based, periodic · CPC title

• G06F9/5038

  considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups) · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title