Highly efficient microdevices

US12464876B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12464876-B2
Application numberUS-202218047920-A
CountryUS
Kind codeB2
Filing dateOct 19, 2022
Priority dateSep 19, 2018
Publication dateNov 4, 2025
Grant dateNov 4, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods and structures are disclosed for highly efficient vertical devices. The vertical device comprising a plurality of planar active layers formed on a substrate, at least one of a top layer of the plurality of the layers is formed as a plurality of nano-pillars and a passivation layer formed on a space between the plurality of the nanopillars.

First claim

Opening claim text (preview).

We claim: 1 . A method to create a vertical device comprising: forming a plurality of planar active layers on a substrate; investigating a surface of the plurality of planar active layers to map one or more defects; using a defect map to control formation of a plurality of nano-pillars on a defective area by adjusting a position of the plurality of nano-pillars, forming at least one of a top layer of the plurality of planar active layers as the plurality of nano-pillars based on the defect map, the plurality of nano-pillars being spaced apart to define a repeating arrangement of nano-pillars, the repeating arrangement of nano-pillars including gaps between the nano-pillars above the one or more defects; forming a first passivation layer comprising a dielectric layer on the top layer of the plurality of planar active layers, the first passivation layer extending in a space between the plurality of nano-pillars and at least on a part of sidewalls of the plurality of nano-pillars; and forming a gate electrode on at least a part of the first passivation layer, wherein the plurality of nano-pillars, the dielectric layer, and the gate electrode act as a vertical transistor in series with the plurality of planar active layers of the vertical device to control current going through the plurality of nano-pillars to the plurality of planar active layers of the vertical device. 2 . The method of claim 1 , wherein the gate electrode extends in the space between the plurality of nano-pillars and on the part of sidewalls of the plurality of nano-pillars. 3 . The method of claim 2 , wherein the gate electrode is formed to bias the plurality of nano-pillars to control a charge accumulated on a surface of the plurality of nano-pillars. 4 . The method of claim 2 , further comprising: forming a second passivation layer over at least a part of the gate electrode; and forming a device electrode over the second passivation layer to create a functional area for the vertical device, wherein the device electrode comprises one of: a filler layer or a reflector. 5 . The method of claim 4 , wherein the device electrode comprises a separate electrode or a part of a nano-contact. 6 . The method of claim 1 , further comprising forming an ohmic contact layer on a top surface of at least one nano-pillar to create at least one nano-contact. 7 . The method of claim 1 , further comprising etching down a conductive layer, a doped layer, or both, formed on the plurality of planar active layers to form the plurality of nano-pillars. 8 . The method of claim 1 , further comprising adjusting a size and a density of the plurality of nano-pillars based on a peak efficiency of the vertical device, wherein the peak efficiency occurs at a maximum value of current density of the vertical device. 9 . The method of claim 1 , wherein the dielectric layer and a conductive layer are configured to spread to other areas of the vertical device. 10 . The method of claim 1 , further comprising forming a filler layer on a top surface of the first passivation layer, the filler layer including one of: a polymer, a solgel, and a dielectric. 11 . The method of claim 10 , wherein the filler layer further includes a color conversion layer.

Assignees

Inventors

Classifications

  • extending at least partially onto an outer side surface of the bodies · CPC title

  • the light-emitting regions comprising nitride materials · CPC title

  • Optical field-shaping means, e.g. lenses · CPC title

  • Electrodes · CPC title

  • Manufacture or treatment · CPC title

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Frequently asked questions

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What does patent US12464876B2 cover?
Methods and structures are disclosed for highly efficient vertical devices. The vertical device comprising a plurality of planar active layers formed on a substrate, at least one of a top layer of the plurality of the layers is formed as a plurality of nano-pillars and a passivation layer formed on a space between the plurality of the nanopillars.
Who is the assignee on this patent?
Vuereal Inc
What technology area does this patent fall under?
Primary CPC classification H10H20/819. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 04 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).