Method of manufacturing a nanostructure light emitting device by planarizing a surface of the device

Patent metadata

Field	Value
Publication number	US-9385266-B2
Application number	US-201414165168-A
Country	US
Kind code	B2
Filing date	Jan 27, 2014
Priority date	Jan 29, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, and a plurality of light emitting nanostructures. The base layer includes a first conductivity type semiconductor. The insulating layer is disposed on the base layer and has a plurality of openings through which regions of the base layer are exposed. The light emitting nanostructures are respectively disposed on the exposed regions of the base layer and include a plurality of nanocores having a first conductivity type semiconductor and having side surfaces provided as the same crystal planes. The light emitting nanostructures include an active layer and a second conductivity type semiconductor layer sequentially disposed on surfaces of the nanocores. Upper surfaces of the nanocores are provided as portions of upper surfaces of the light emitting nanostructures, and the upper surfaces of the light emitting nanostructures are substantially planar with each other.

First claim

What is claimed is:

1. A method of manufacturing a core-shell structure semiconductor light emitting device, the method comprising:
growing, by using a first conductivity type semiconductor, a plurality of cores on selective portions of a base layer including the first conductivity type semiconductor, such that each of the plurality of cores includes a main part that has a side surface having a first crystal plane in a growth direction and an upper part that has a surface having a second crystal plane different from the first crystal plane;
forming a plurality of light emitting core-shell structures by sequentially growing a shell including an active layer and a second conductivity type semiconductor layer on surfaces of the respective cores;
forming a contact electrode on a surface of the second conductivity type semiconductor layer; and
planarizing a surface of the core-shell structure semiconductor light emitting device in which the contact electrode is disposed, so as to remove a portion of the active layer disposed on the second crystal plane,
wherein the growing of the plurality of cores comprises growing at least a group of cores among the plurality of cores to have cross-sectional areas or an interval therebetween different from cross-sectional areas of or an interval between another group of cores among the plurality of cores.

2. The method of claim 1 , wherein the growing of the plurality of cores includes:
providing the base layer formed of the first conductivity type semiconductor;
forming, on the base layer, a mask including a plurality of layers including an etch stop layer;
forming, in the mask, a plurality of openings through which regions of the base layer are exposed;
forming the plurality of cores by growing the first conductivity type semiconductor on the exposed regions of the base layer so as to fill the plurality of openings with the first conductivity type semiconductor; and
partially removing the mask by using the etch stop layer to expose the side surfaces of the plurality of cores.

3. The method of claim 2 , wherein the mask includes a first material layer disposed on the base layer and serving as the etch stop layer, and a second material layer disposed on the first material layer and having an etching rate lower than an etching rate of the first material layer.

4. The method of claim 2 , wherein:
the mask includes first to third material layers sequentially disposed on the base layer, and
the second material layer includes a material different from materials of the first and third material layers and serves as the etch stop layer.

5. The method of claim 2 , further comprising:
heat treating the plurality of cores after the partially removing of the mask and before the sequentially growing of the active layer and the second conductivity type semiconductor layer.

6. The method of claim 5 , wherein the heat treating of the plurality of cores is performed at a temperature ranging from 800 to 1200° C.

7. The method of claim 2 , further comprising:
applying a planarizing process to upper surfaces of the plurality of cores to be planarized to have an identical level, after the forming of the plurality of cores.

8. A method of manufacturing a core-shell structure semiconductor light emitting device, the method comprising:
growing, by using a first conductivity type semiconductor, a plurality of cores on selective portions of a base layer including the first conductivity type semiconductor, such that each of the plurality of cores includes a main part that has a side surface having a first crystal plane in a growth direction and an upper part that has a surface having a second crystal plane different from the first crystal plane;
forming a plurality of light emitting core-shell structures by sequentially growing a shell including an active layer and a second conductivity type semiconductor layer on surfaces of the respective cores;
forming a contact electrode on a surface of the second conductivity type semiconductor layer; and
planarizing a surface of the core-shell structure semiconductor light emitting device in which the contact electrode is disposed, so as to remove a portion of the active layer disposed on the second crystal plane,
wherein the growing of the plurality of cores includes:
providing the base layer formed of the first conductivity type semiconductor;
forming, on the base layer, a mask including a plurality of layers including an etch stop layer;
forming, in the mask, a plurality of openings through which regions of the base layer are exposed;
forming the plurality of cores by growing the first conductivity type semiconductor on the exposed regions of the base layer so as to fill the plurality of openings with the first conductivity type semiconductor; and
partially removing the mask by using the etch stop layer to expose the side surfaces of the plurality of cores.

9. The method of claim 8 , wherein the mask includes a first material layer disposed on the base layer and serving as the etch stop layer, and a second material layer disposed on the first material layer and having an etching rate lower than an etching rate of the first material layer.

10. The method of claim 8 , wherein:
the mask includes first to third material layers sequentially disposed on the base layer, and
the second material layer includes a material different from materials of the first and third material layers and serves as the etch stop layer.

11. The method of claim 8 , further comprising:
heat treating the plurality of cores after the partially removing of the mask and before the sequentially growing of the active layer and the second conductivity type semiconductor layer.

12. The method of claim 11 , wherein the heat treating of the plurality of cores is performed at a temperature ranging from 800 to 1200° C.

13. The method of claim 8 , further comprising:
applying a planarizing process to upper surfaces of the plurality of cores to be planarized to have an identical level, after the forming of the plurality of cores.

14. The method of claim 8 , wherein at least a group of cores among the plurality of cores have cross-sectional areas or an interval therebetween different from cross-sectional areas of or an interval between another group of cores among the plurality of cores.

15. A method of manufacturing a core-shell structure semiconductor light emitting device, the method comprising:
growing, by using a first conductivity type semiconductor, a plurality of cores on selective portions of a base layer including the first conductivity type semiconductor, such that each of the plurality of cores includes a main part that has a side surface having a first crystal plane in a growth direction and an upper part that has a surface having a second crystal plane different from the first crystal plane;
forming a plurality of light emitting core-shell structures by sequentially growing a shell including an active layer and a second conductivity type semiconductor layer on surfaces of the respective cores;
forming a contact electrode on a surface of the second conductivity type semiconductor layer by homogeneously filling a space between the plurality of light emitting core-shell structures with an electrode material to cover the plurality of light emitting core-shell structures; and
planarizing upper surfaces of the plurality of light emitting core-shell structures so as to expose upper surfaces of the plurality of the cores,
wherein the growing of the plurality of cores includes:
providing the base layer formed of the first conductivity type semiconductor;
forming, o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Nam Goo
• Kim Dong Ho
• Yoo Geon Wook

Classifications

• H10H20/8316

  Multi-layer electrodes comprising at least one discontinuous layer · CPC title

• H10H20/8312

  extending at least partially through the bodies · CPC title

• H10H20/034

  of coatings · CPC title

• H10H20/032

  of electrodes · CPC title

• H10H20/01335

  the light-emitting regions comprising nitride materials · CPC title