Highly efficient microdevices

Patent metadata

Field	Value
Publication number	US-12464875-B2
Application number	US-202218047903-A
Country	US
Kind code	B2
Filing date	Oct 19, 2022
Priority date	Sep 19, 2018
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Methods and structures are disclosed for highly efficient vertical devices. The vertical device comprising a plurality of planar active layers formed on a substrate, at least one of a top layer of the plurality of the layers is formed as a plurality of nano-pillars and a passivation layer formed on a space between the plurality of the nanopillars.

First claim

We claim:

1 . A vertical device comprising:
a plurality of planar active layers formed on a substrate, at least one layer of the plurality of planar active layers including one or more defects; a plurality of nano-pillars on a top layer of the plurality of planar active layers that are spaced apart to define a repeating arrangement of nano-pillars, nano-pillars in the repeating arrangement of nano-pillars defined by a predetermined radius and separated by a predetermined distance; a first passivation layer comprising a dielectric layer formed on the top layer of the plurality of planar active layers covering a space between the plurality of nano-pillars and at least a part of sidewalls of the plurality of nano-pillars, wherein the first passivation layer covers one or more gaps in the top layer of the plurality of planar active layers corresponding to the one or more defects; and a gate electrode comprising a conductive layer formed on a part of the first passivation layer covering at least in part the space between the plurality of nano-pillars and the part of the sidewalls of the plurality of nano-pillars covered by the first passivation layer, wherein the gate electrode is configured to bias the plurality of nano-pillars to control a charge accumulated on a surface of the plurality of nano-pillars or a current passing through the plurality of nano-pillars to the plurality of planar active layers such that the gate electrode, the first passivation layer, and the plurality of nano-pillars act as a vertical transistor in series with the plurality of planar active layers of the vertical device.

2 . The vertical device of claim 1 , further comprising:
a second passivation layer formed over the gate electrode; and a device electrode formed over the second passivation layer to create a functional area for the vertical device, wherein the device electrode comprises one of: a filler layer or a reflector.

3 . The vertical device of claim 2 , further comprising:
an ohmic contact layer formed on a top surface of at least one nano-pillar of the plurality of nano-pillars to create one or more nano-contacts.

4 . The vertical device of claim 3 , wherein the device electrode comprises a separate electrode or a part of the one or more nano-contacts.

5 . The vertical device of claim 1 , wherein the plurality of nano-pillars is formed by etching down at least one planar layer formed on top of the plurality of planar active layers formed on the substrate.

6 . The vertical device of claim 1 , wherein the dielectric layer and the conductive layer are configured to spread to other areas of the vertical device.

7 . The vertical device of claim 1 , further comprising:
a filler layer formed on a top surface of the first passivation layer or formed on the top layer of the plurality of planar active layers instead of the first passivation layer, the filler layer including one of: a polymer, a solgel, and a dielectric.

8 . The vertical device of claim 7 , wherein the filler layer further includes a color conversion layer.

9 . A vertical device comprising:
a substrate; a plurality of planar active layers formed on the substrate; a plurality of nano-pillars comprising a doped layer coupled to the plurality of planar active layers, at least a portion of the doped layer being thinned to form the plurality of nano-pillars; a passivation layer comprising a dielectric layer formed on a top layer of the plurality of planar active layers, the dielectric layer covering a space between the plurality of nano-pillars and a part of sidewalls of the plurality of nano-pillars; and a gate electrode comprising a conductive layer formed at least on a part of the passivation layer covering the space between the plurality of nano-pillars and the part of the sidewalls of the plurality of nano-pillars, wherein the gate electrode is configured to bias the plurality of nano-pillars to control a charge accumulated on a surface of the plurality of nano-pillars or a current passing through the plurality of nano-pillars to the plurality of planar active layers such that the gate electrode, the passivation layer, and the plurality of nano-pillars act as a vertical transistor in series with the plurality of planar active layers of the vertical device.

Assignees

• Vuereal Inc

Inventors

• Chaji Gholamreza
• Fathi Ehsanollah
• Li Yunhan
• Siboni Hossein Zamani

Classifications

• H10H20/8314

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• H10H20/0137

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• H10H20/855

  Optical field-shaping means, e.g. lenses · CPC title

• H10H20/83

  Electrodes · CPC title

• H10H20/01

  Manufacture or treatment · CPC title