Semiconductor device with reduced stress die pick and place

US12463097B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12463097-B2
Application numberUS-202117174802-A
CountryUS
Kind codeB2
Filing dateFeb 12, 2021
Priority dateDec 3, 2020
Publication dateNov 4, 2025
Grant dateNov 4, 2025

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Semiconductor dies formed on a wafer may be picked from the wafer with little or no stress, thus preventing cracking and damage to the semiconductor dies. A die attach film (DAF) layer is laminated onto an inactive surface of the wafer and the DAF layer is cut in the outline of the dies. The inactive surface of the wafer may then be supported on a vacuum chuck without using a dicing tape, and dies transferred from the wafer using a pick and place robot.

First claim

Opening claim text (preview).

We claim: 1 . A method of separating a semiconductor die from a semiconductor wafer, comprising the steps of: applying a die attach film adhesive to a surface of the semiconductor wafer; supporting the semiconductor wafer on a vacuum chuck, with a surface of the die attach film in direct contact with the vacuum chuck; cutting the die attach film around an outline of the semiconductor die with a laser after applying the die attach film to the semiconductor die; removing the semiconductor die from the wafer, said step of removing the semiconductor die from the wafer comprising the step of applying a first vacuum force to the surface of the die attach film while a second vacuum force is applied to one or more semiconductor dies around the semiconductor die, where the second vacuum force is greater than the first vacuum force; and transferring the semiconductor die into the semiconductor device. 2 . The method of claim 1 , further comprising the step of partially cutting the wafer around the semiconductor die through a first major surface of the wafer, and completing the separation of the semiconductor die from the wafer by thinning the wafer from a second major surface of the semiconductor wafer, before applying the die attach film to the second major surface. 3 . The method of claim 1 , wherein the step of removing the semiconductor die from the wafer comprises the step of overcoming an adhesive force between the die attach film and the vacuum chuck. 4 . The method of claim 1 , wherein the step of removing the semiconductor die from the wafer comprises the step of gripping a first surface of the semiconductor die with the tip of a pick and place robot. 5 . The method of claim 4 , wherein the step of removing the semiconductor die from the wafer comprises the step of exerting a negative pressure against semiconductor dies around the semiconductor die being removed. 6 . The method of claim 1 , wherein the step of supporting the semiconductor wafer on the vacuum chuck comprises the step of supporting the wafer on a vacuum chuck configured to supply a positive or negative pressure to the semiconductor die independently of other semiconductor dies in the wafer. 7 . A method of assembling a semiconductor device, comprising the steps of: applying a die attach film as a B-stage adhesive to a surface of a semiconductor wafer, the wafer comprising a number of semiconductor dies; cutting through the die attach film around outlines of the semiconductor dies; after cutting through the die attach film, turning the wafer over and supporting the semiconductor wafer on a vacuum chuck, with the die attach film lying against the vacuum chuck; removing a semiconductor die from the wafer with a pick and place robot; transferring the semiconductor die into the semiconductor device; curing the die attach film to a C-stage adhesive to secure the semiconductor die within the semiconductor device. 8 . The method of claim 7 , further comprising the step of cutting the die attach film around an outline of the semiconductor die after applying the die attach film to the semiconductor die. 9 . The method of claim 7 , wherein the step of removing the semiconductor die from the wafer comprises the step of overcoming an adhesive force between the die attach film and the vacuum chuck. 10 . The method of claim 7 , wherein the step of removing the semiconductor die from the wafer comprises the step of exerting a negative pressure against semiconductor dies around the semiconductor die being removed. 11 . The method of claim 10 , wherein the step of removing the semiconductor die from the wafer comprises the step of blowing a fluid against the semiconductor die being removed, while the negative pressure is exerted on the semiconductor dies around the semiconductor die being removed. 12 . The method of claim 7 , wherein the step of supporting the semiconductor wafer on a vacuum chuck comprises the step of supporting the wafer on a vacuum chuck configured to supply a positive or negative pressure to the semiconductor die independently of other semiconductor dies in the wafer.

Assignees

Inventors

Classifications

  • Materials of bond wires · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • hardening the adhesive by curing, e.g. thermosetting · CPC title

  • of die-attach connectors · CPC title

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Frequently asked questions

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What does patent US12463097B2 cover?
Semiconductor dies formed on a wafer may be picked from the wafer with little or no stress, thus preventing cracking and damage to the semiconductor dies. A die attach film (DAF) layer is laminated onto an inactive surface of the wafer and the DAF layer is cut in the outline of the dies. The inactive surface of the wafer may then be supported on a vacuum chuck without using a dicing tape, and d…
Who is the assignee on this patent?
Sandisk Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/78. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 04 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).