Semiconductor substrate, and manufacturing method and manufacturing apparatus of semiconductor substrate

Patent metadata

Field	Value
Publication number	US-12463033-B2
Application number	US-202218038193-A
Country	US
Kind code	B2
Filing date	Oct 19, 2022
Priority date	Oct 19, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A template substrate including a first seed region and a growth restricting region that are aligned in a first direction, and a first semiconductor part positioned above the template substrate are provided, the first semiconductor part includes a first base positioned above the first seed region, and a first wing connected to the first base, the first wing facing the growth restricting region with a first void space interposed therebetween, the first wing includes an edge positioned above the growth restricting region, and a ratio of a width of the first void space with respect to a thickness of the first void space in the first direction is equal to or larger than 5.0.

First claim

The invention claimed is:

1 . A semiconductor substrate comprising:
a template substrate comprising a first seed region, a growth restricting region, and a second seed region that are aligned in a first direction in a plan view; a first semiconductor part that is positioned above the template substrate and connected to the first seed region; and a second semiconductor part that is positioned above the template substrate and connected to the second seed region, wherein
the first semiconductor part comprises (i) a first base, which is in contact with the template substrate and defined by a vertically extending section of the first semiconductor part that contacts the template substrate, and (ii) a first wing which is not in contact with the template substrate, is adjacent to the first base, and extends from the first base in the first direction,
the first wing comprises a wing edge which is positioned above and suspended over the growth restricting region and is spaced apart from the second semiconductor part by a gap interposed between the wing edge and the second semiconductor part,
the gap being configured to prevent physical contact between the first wing and the second semiconductor part,
the growth restricting region comprises a top surface on an upper side of the template substrate, the top surface having a first portion that faces the first wing, and
a first ratio, which is defined by a width of the first wing in the first direction divided by a shortest vertical distance from the first portion of the top surface of the growth restricting region to the wing edge, is equal to or larger than 5.0.

2 . The semiconductor substrate according to claim 1 ,
wherein a width of the gap in the first direction is larger than the shortest vertical distance from the first portion of the top surface of the growth restricting region to the wing edge.

3 . The semiconductor substrate according to claim 2 , wherein
the width of the first wing in the first direction is equal to or larger than 7.0 μm.

4 . The semiconductor substrate according to claim 1 , wherein
the second semiconductor part comprises (i) a second base, which is in contact with the template substrate and defined by a vertically extending section of the second semiconductor part that contacts the template substrate, and (ii) a second wing which is not contact with the template substrate, is adjacent to the second base, and extends from the second base in the first direction.

5 . The semiconductor substrate according to claim 1 , wherein
the template substrate comprises a ridge part on an upper surface side, and the first seed region is positioned on an upper surface of the ridge part.

6 . The semiconductor substrate according to claim 1 , wherein
a second ratio, which is defined by the width of the first wing in the first direction divided by a width of the first base in the first direction, is equal to or larger than 3.0.

7 . The semiconductor substrate according to claim 1 , wherein
a thickness of the first wing and a thickness of the first base are equal.

8 . The semiconductor substrate according to claim 1 , wherein
a thickness of the first wing is larger than a thickness of the first base.

9 . The semiconductor substrate according to claim 1 , wherein
the shortest vertical distance from the first portion of the top surface of the growth restricting region to the wing edge is equal to or smaller than 3.0 μm.

10 . The semiconductor substrate according to claim 1 , wherein
each of the first seed region and the growth restricting region has a shape that extends in a longitudinal direction, the longitudinal direction being a second direction orthogonal to the first direction.

11 . The semiconductor substrate according to claim 1 , wherein
the template substrate comprises
a main substrate having a lattice constant different from a lattice constant of the first semiconductor part, and
a seed part.

12 . The semiconductor substrate according to claim 11 , wherein
the main substrate is a silicon substrate, a sapphire substrate, or a silicon carbide substrate, and the first semiconductor part comprises a nitride semiconductor.

13 . The semiconductor substrate according to claim 11 , wherein
the template substrate comprises
a mask pattern including a mask part functioning as the growth restricting region, and
an opening portion functioning as the first seed region.

14 . The semiconductor substrate according to claim 13 , wherein
the template substrate comprises a ridge part on an upper surface side, and the ridge part comprises the seed part.

15 . The semiconductor substrate according to claim 14 , wherein
the seed part is not disposed under the mask part.

16 . The semiconductor substrate according to claim 14 , wherein
an upper surface of the ridge part is formed by the seed part, and a side surface of the ridge part is formed by the mask part.

17 . The semiconductor substrate according to claim 14 , wherein
the main substrate comprises a protruding portion on the upper surface side, and the seed part is positioned on the protruding portion.

18 . The semiconductor substrate according to claim 14 , wherein
the ridge part is positioned on an upper surface of the main substrate, the upper surface being flat.

19 . The semiconductor substrate according to claim 16 , wherein
the side surface of the ridge part is in contact with the first base.

20 . The semiconductor substrate according to claim 13 , wherein
a thickness of the mask part is equal to or smaller than 50 nm.

21 . The semiconductor substrate according to claim 12 , wherein
the nitride semiconductor is a GaN-based semiconductor, and the first ratio is equal to or larger than 20.0.

22 . The semiconductor substrate according to claim 1 , wherein
the first semiconductor part comprises a pair of two first wings extending from the first base individually in the first direction and in a direction opposite to the first direction.

23 . The semiconductor substrate according to claim 1 , further comprising:
an upper layer part positioned above the first semiconductor part, the upper layer part comprising an active layer and a p-type layer.

24 . The semiconductor substrate according to claim 11 , wherein
an upper surface of the seed part is the first seed region, a side surface of the seed part is covered with a same material as a material of the growth restricting region.

25 . The semiconductor substrate according to claim 1 , wherein
a third ratio, which is defined by the width of the first wing in the first direction divided by a thickness of the first wing in a direction orthogonal to the first direction, is equal to or larger than 5.0.

Assignees

• Kyocera Corp

Inventors

• Kamikawa Takeshi
• Aoki Yuta
• Takeuchi Kazuma
• Masaki Katsuaki
• Yamashita Fumio

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/278

  Pendeoepitaxy · CPC title

• H10P14/3416 Primary

  Nitrides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title