Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

Patent metadata

Field	Value
Publication number	US-10930500-B2
Application number	US-201916431646-A
Country	US
Kind code	B2
Filing date	Jun 4, 2019
Priority date	Sep 18, 2014
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

First claim

What is claimed is:

1. A device structure, comprising:
a substrate comprising a crystalline Group IV material;
a dielectric material over the substrate;
a body comprising one or more Group III-N materials having hexagonal crystallinity, wherein the body comprises a first portion in contact with a (100) crystal plane of the Group IV material, and adjacent to a sidewall of the dielectric material that extends laterally in a <110> direction over the (100) crystal plane, and wherein the body comprises a second portion separated from the crystal plane by the first portion, wherein the second portion has a thickness over the first portion and over a top surface of the dielectric material a lateral distance beyond the sidewall of the dielectric material, wherein a c-plane of the Group III-N materials is substantially parallel to the (100) crystal plane of the Group IV material, and
one or more terminals over the second portion of the body and substantially parallel to the c-plane, wherein the thickness of the second portion comprises an upper portion over a lower portion, the upper portion with lower defect density than the lower portion.

2. The device structure of claim 1 , wherein the terminals comprise a gate electrode.

3. The device structure of claim 2 , wherein the terminals further comprise a source terminal and a drain terminal on opposite sides of the gate electrode.

4. The device structure of claim 1 , wherein the c-plane is no more than 10° from parallel to the (100) crystal plane of the Group IV material, and the second portion comprises an inclined sidewall having a slope of 50-80 degrees relative to the top surface of the dielectric material.

5. The device structure of claim 4 , wherein a top surface of the second portion of the body has a lower defect density than the inclined sidewall.

6. The device structure of claim 1 , wherein the terminals comprise a first electrode of a diode.

7. The device structure of claim 1 , further comprising a MOSFET over a portion of the substrate adjacent to the body, wherein the MOSFET includes a source and a drain with a gate electrode therebetween, wherein the source and the drain are coupled through a channel length of the Group IV material.

8. The device structure of claim 1 , wherein the first portion of the body is one of a plurality of first portions, each first portion separated from adjacent ones of the plurality by the dielectric material with the second portion over each of the plurality of first portions, and over the dielectric material between the first portions.

9. The device structure of claim 1 , wherein the thickness is at least

√
3

2

times a lateral width of the first portion.

10. The semiconductor heterostructure of claim 1 , wherein:
the Group IV material is silicon; and
the Group III-N materials comprise at least GaN.

11. A device structure, comprising:
a substrate comprising a crystalline Group IV material;
a dielectric material over the substrate;
a body comprising one or more Group III-N materials having hexagonal crystallinity, wherein a c-plane of the body is substantially parallel to a (100) crystal plane of the Group IV material, wherein the body comprises a plurality of first portions between the (100) crystal plane of the Group IV material and a second portion of the body, wherein individual ones of the plurality first portions have a sidewall adjacent to the dielectric material, and are separated from each other by the dielectric material, and wherein the second portion is over a top surface of the dielectric material, and wherein the body comprises a plurality of third portions between the second portion of the body and a fourth portion of the body, wherein individual ones of the plurality of third portions have a sidewall adjacent to a second dielectric material, and are separated from each other by the second dielectric material, and wherein the fourth portion is over a top surface of the second dielectric material; and
one or more terminals over the fourth portion of the body, and substantially parallel to the c-plane.

12. The device structure of claim 11 , wherein the terminals comprise a source and drain on opposite sides of a gate electrode.

13. The device structure of claim 12 , wherein a top surface of the fourth portion of the body is substantially parallel to a c-plane of the Group III-N material and the gate electrode is over a top surface of the fourth portion of the body.

14. The device structure of claim 13 , wherein the c-plane is no more than 10° from parallel to a (100) plane of the substrate.

15. The device structure of claim 14 , wherein the top surface of the fourth portion of the body has a lower defect density than the second portion of the body.

16. A system, comprising:
a power supply; and
an integrated circuit (IC) coupled to receive power from the power supply, wherein the IC comprises a transistor having the device structure of claim 1 .

17. The system of claim 16 , wherein the IC is a system-on-chip (SoC) further comprising MOSFETs having a silicon channel.

18. The system of claim 16 , wherein the system is to display, process and wirelessly transmit electronic data.

Assignees

• Intel Corp

Inventors

• Dasgupta Sansaptak
• Then Han Wui
• Chu-Kung Benjamin
• Radosavljevic Marko
• Gardner Sanaz K
• Sung Seung Hoon
• Pillarisetty Ravi
• Chau Robert S

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2905 Primary

  Silicon, silicon germanium or germanium · CPC title