Iii-n epitaxial device structures on free standing silicon mesas

Patent metadata

Field	Value
Publication number	US-2018219087-A1
Application number	US-201415505911-A
Country	US
Kind code	A1
Filing date	Sep 25, 2014
Priority date	Sep 25, 2014
Publication date	Aug 2, 2018
Grant date	—

Abstract

III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

First claim

1 - 25 . (canceled)

26 . A semiconductor heterostructure, comprising:
a pair of silicon mesas disposed in a first region of a silicon substrate; a pair of III-N epitaxial islands disposed on top surfaces of the mesas with the c-axis of the islands substantially orthogonal to the top mesa surfaces, each island including a core region, and a peripheral region surrounding the core and extending laterally beyond sidewalls of the silicon mesa, the peripheral region having n-plane sidewalls separated by a non-zero spacing; and one or more III-N epitaxial semiconductor device layer disposed over the III-N epitaxial islands, covering at least the (0001) and (000-1) surfaces of the peripheral region.

27 . The semiconductor heterostructure of claim 26 , wherein:
the mesas extend from the substrate by a z-height that is at least 500 nm; the III-N epitaxial islands have a greatest z-thickness over the mesa top surface that is no more than 500 nm; the peripheral regions extend laterally beyond the sidewalls by at least 500 nm; and the one or more semiconductor device layer comprises a polarization layer having a composition that induces a 2D electron gas (2DEG) in a first channel region of the peripheral region.

28 . The semiconductor heterostructure of claim 27 , wherein:
the smallest lateral width of the mesa is between 500 nm and 1 μm; the mesas extend from the substrate by a z-height that is between 750 nm and 5 μm; and the one or more semiconductor device layer comprises:
a polarization layer having a composition sufficiently distinct from that of the III-N islands to induce a first 2D electron gas (2DEG) within the peripheral region; and
a second III-N semiconductor layer disposed over the polarization layer and having a composition sufficiently distinct from that of the polarization layer to maintain a second 2DEG within the second III-N semiconductor layer.

29 . The semiconductor heterostructure of claim 26 , wherein the III-N island core has at least a first density of threading dislocations extending from the top mesa surface through a z-height of the islands, and wherein the peripheral region has a threading dislocation density that is at least an order of magnitude lower than the first density.

30 . The semiconductor heterostructure of claim 26 , wherein the one or more epitaxial semiconductor device layer is further disposed on the m-plane sidewalls of the III-N islands.

31 . The semiconductor heterostructure of claim 26 , wherein the silicon mesas are undercut to have a lateral width proximal to the III-N island that is smaller than that of the III-N island core, an undercut portion of the III-N island substantially free of the one or more III-N semiconductor device layers.

32 . The semiconductor heterostructure of claim 26 , wherein:
the smallest lateral width of the mesa is between 500 nm and 5 μm; the mesas extend from the substrate by a z-height that is between 750 nm and 5 μm; the peripheral regions extend laterally beyond the sidewalls by at least 500 nm; the substrate includes a second region adjacent to the first region, the second substrate region having a substantially planar top surface at a z-height relative to a bottom of the mesas that is greater than the z-height of the mesas; the III-N island comprises GaN with the c-plane no more than 10° from parallel to a (100) plane of the substrate; the one or more semiconductor device layer comprises a polarization layer having a composition sufficiently distinct from GaN to induce a first 2D electron gas (2DEG) within the GaN peripheral region; the one or more epitaxial semiconductor device layer is further disposed on the n-plane sidewalls of the III-N islands.

33 . A semiconductor heterostructure, comprising:
a pair of III-N epitaxial islands disposed on a transfer substrate with the (0001) surface of the islands proximal to the transfer substrate and the (000-1) surface of the islands distal from the transfer substrate, wherein:
each island including a core region and a peripheral region surrounding the core, the pair of islands having n-plane sidewalls separated by a non-zero spacing;
the III-N island cores have at least a first density of threading dislocations extending from the top mesa surface through a z-height of the islands, and wherein the peripheral region has a threading dislocation density that is at least an order of magnitude lower than the first density; and
one or more III-N epitaxial semiconductor device layer disposed over the III-N epitaxial islands, covering at least the (0001) and (000-1) surfaces of the peripheral region.

34 . The semiconductor heterostructure of claim 33 , wherein:
the one or more III-N epitaxial semiconductor device layer is disposed between the transfer substrate and both the III-N epitaxial island core and peripheral regions; the (000-1) surface of the core region is substantially free of the at least one of the one or more III-N epitaxial semiconductor device layer covering the (000-1) surface of the peripheral region.

35 . A semiconductor device, comprising:
a semiconductor heterostructure including:
a pair of silicon mesas disposed in a first region of a silicon substrate;
a pair of III-N epitaxial islands disposed on top surfaces of the mesas with the c-axis of the islands substantially orthogonal to the top mesa surfaces, each island including a core region and an peripheral region extending lateral from the core and beyond sidewalls of the silicon mesa, and the peripheral regions having n-plane sidewalls separated by a non-zero spacing; and
one or more III-N epitaxial semiconductor device layer disposed over the III-N epitaxial islands, covering at least the (0001) and (000-1) surfaces of the peripheral region; and
one or more device terminal coupled to the one or more semiconductor device layers within the peripheral region.

36 . The device of claim 35 , wherein:
the polarization layer has a composition that induces a 2D electron gas (2DEG) in a first channel region of the peripheral region; and the one or more device terminal further comprises a gate terminal disposed between a pair of source/drain terminals, at least the gate terminal disposed within the peripheral region and operable to modulate the 2DEG.

37 . The device of claim 36 , wherein:
the one or more III-N epitaxial semiconductor device layer includes:
the polarization layer disposed over a (0001) surface of the III-N island;
a second III-N semiconductor device layer disposed over a (000-1) surface of the polarization layer and having a composition sufficiently distinct from that of the polarization layer to maintain a second 2DEG within the second III-N semiconductor device layer; and
the one or more device terminal further comprises a second gate terminal disposed between a second pair of source/drain terminals, at least the second gate terminal disposed within the peripheral region and operable to modulate the second 2DEG.

38 . The device of claim 35 , wherein:
the one or more III-N epitaxial semiconductor device layer further comprises a light emitting diode (LED) stack disposed over the III-N epitaxial islands, covering at least the (0001) and (000-1) surface of the peripheral region; and the one or more device terminal includes:
a first terminal disposed on at least the (0001) surface of the device layer; and
a second terminal disposed on at least the (000-1) surface of the device layer.

39 . A method of forming a semiconductor heterostructure, the method comprising:
forming a pair of silicon mesas in a first region of a silicon substrate; epitaxially growing a co

Assignees

• Intel Corp

Inventors

• Dasgupta Sansaptak
• Then Han Wui
• Gardner Sanaz K
• Radosavljevic Marko
• Sung Seung Hoon
• Chu-Kung Benjamin
• Chau Robert S

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/278

  Pendeoepitaxy · CPC title