3D printed semiconductor package

Patent metadata

Field	Value
Publication number	US-12457756-B2
Application number	US-202418404496-A
Country	US
Kind code	B2
Filing date	Jan 4, 2024
Priority date	Dec 28, 2018
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

In described examples, an integrated circuit comprises: a substrate; a semiconductor die on the substrate; and a device on the substrate and electrically coupled to the semiconductor die, the device including a polymer structure coated with a metal.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
a semiconductor die on the substrate; and
a device on the semiconductor die and electrically coupled to the semiconductor die, in which the semiconductor die is between the device and the substrate, and the device includes a polymer structure coated with a metal.

2. The integrated circuit of claim 1 , further comprising an encapsulation material encapsulating the semiconductor die and the device.

3. The integrated circuit of claim 2 , wherein the encapsulation material includes a resin.

4. The integrated circuit of claim 2 , wherein the encapsulation material encapsulates a cavity around at least a part of the device.

5. The integrated circuit of claim 1 , wherein the device includes an inductor.

6. The integrated circuit of claim 1 , wherein the device includes an antenna.

7. The integrated circuit of claim 1 , wherein the substrate includes a package substrate.

8. The integrated circuit of claim 1 , wherein the substrate includes a lead frame.

9. The integrated circuit of claim 1 , wherein the metal is coated with an insulator.

10. The integrated circuit of claim 1 , wherein the polymer structure includes layers of polymerized liquid polymer material.

11. The integrated circuit of claim 1 , wherein the polymer structure includes resin.

12. An integrated circuit comprising:
a substrate;
a semiconductor die on the substrate; and
a device on the semiconductor die and electrically coupled to the semiconductor die, in which the semiconductor die is between the substrate and the device, and the device includes a polymerized material coated with a metal.

13. The integrated circuit of claim 12 , wherein the polymerized material is a solid polymerized resin.

14. The integrated circuit of claim 12 , further comprising an encapsulation material encapsulating the semiconductor die and the device.

15. The integrated circuit of claim 14 , wherein the encapsulation material encapsulates a cavity around at least a part of the device.

16. The integrated circuit of claim 12 , wherein the device includes an inductor.

17. The integrated circuit of claim 12 , wherein the device includes an antenna.

18. The integrated circuit of claim 12 , wherein the substrate includes a package substrate.

19. The integrated circuit of claim 12 , wherein the substrate includes a lead frame.

20. The integrated circuit of claim 12 , wherein the metal is coated with an insulator.

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Revier Daniel Lee

Classifications

• H10W44/248

  for antennas · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title