Nested delta-sigma analog-to-digital conversion system and method

Patent metadata

Field	Value
Publication number	US-12456989-B2
Application number	US-202418433541-A
Country	US
Kind code	B2
Filing date	Feb 6, 2024
Priority date	Mar 17, 2023
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A nested Δ-Σ analog-to-digital conversion system and method, compromising: an analog filter, an analog comparator, a first feedback digital-to-analog converter (DAC), a second feedback DAC placed in front of the first feedback DAC, and a digital filter and an MSB quantizer placed at the output of the analog comparator; wherein the input of the first feedback DAC is connected to the output of the analog comparator; the analog filter, the analog comparator, and the first feedback DAC form an internal analog Δ-Σ loop; the input of the second feedback DAC is connected to the output of the MSB quantizer; the output of the second feedback DAC is connected to the output of the first feedback DAC and to the input of the analog filter; and the second feedback DAC, the internal analog Δ-Σ loop, the digital filter, and the MSB quantizer form an external hybrid Δ-Σ loop.

First claim

What is claimed is:

1 . A nested Δ-Σ analog-to-digital conversion system comprises: an analog filter, an analog comparator, a first feedback digital-to-analog converter (DAC), a second feedback digital-to-analog converter placed in front of the first feedback digital-to-analog converter, and a digital filter and a most significant bit (MSB) quantizer placed at an output of the analog comparator, which are sequentially connected, and wherein an input of the first feedback digital-to-analog converter is connected to the output of the analog comparator; the analog filter, the analog comparator, and the first feedback digital-to-analog converter form an internal analog Δ-Σ loop; an input of the second feedback digital-to-analog converter is connected to an output of the MSB quantizer; an output of the second feedback digital-to-analog converter is connected to an output of the first feedback digital-to-analog converter and to an input of the analog filter; and the second feedback digital-to-analog converter, the internal analog Δ-Σ loop, the digital filter, and the MSB quantizer form an external hybrid Δ-Σ loop.

2 . The nested Δ-Σ analog-to-digital conversion system according to claim 1 , characterized in that the MSB quantizer comprises: a tri-state digital comparator and an up-down accumulator.

3 . The nested Δ-Σ analog-to-digital conversion system according to claim 2 , characterized in that operating states of the tri-state digital comparator comprises: when an input D of the tri-state digital comparator, is greater than the comparison threshold D H , the tri-state digital comparator outputs +1; when the input D of the tri-state digital comparator, is less than a comparison threshold D L , the tri-state digital comparator outputs- 1 ; when the input D of the tri-state digital comparator, is between D L and D H , the tri-state comparator produces no output.

4 . The nested Δ-Σ analog-to-digital conversion system according to claim 1 , characterized in that the internal analog Δ-Σ loop quantizes an input difference (IN−YA) and outputs a signal V=STF*(IN−YA), wherein STF is a signal transfer function of the internal analog Δ-Σ loop, and due to the high gain characteristics of the digital filter, the input of the digital filter that is the output of the internal analog Δ-Σ loop, is a virtual ground terminal, and the output signal V of the internal analog Δ-Σ loop has only two states of signals, ‘0’ and ‘1’, and when the output signal V deviates from the mean value ½, the MSB quantizer will detect the deviation, and more specifically, when the mean value of the output signal V is higher than D H /lower than D L , the MSB quantizer will increase/decrease the YA in order to decrease/increase (IN-YA), forcing the mean value of V back to ½, and only when the change in the mean value of the output signal V is sufficiently large and outside the range of (D L , D H ) can a change in the output of the MSB quantizer be caused, wherein D H and d L are the high and low thresholds, respectively, of the tri-state comparator of the MSB quantizer.

5 . The nested Δ-Σ analog-to-digital conversion system according to claim 1 , characterized in that output signals of the external hybrid

Δ
-

∑

loop
⁢

Y

=

IN
×
STF
×
L
⁢
P
⁢

F
DIG

+

E
Q

×
N
⁢
T
⁢
F
×
L
⁢
P
⁢

F
DIG

+

E
Y

S
⁢
T
⁢
F
×
L
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DIG

+
1

,

wherein: IN is the input of the nested Δ-Σ analog-to-digital conversion system that is the input analog signal of the external hybrid Δ-Σ loop; Y is the output signal of the internal analog Δ-Σ loop, LPF DIG is the transfer function of the digital filter; E Y is the quantization noise in the quantization process of the MSB; E Q is the quantization noise of the internal analog Δ-Σ loop; NTF is the noise transfer function of the internal analog Δ-Σ loop; and STF is the signal transfer function of the internal analog Δ-Σ loop.

6 . The nested Δ-Σ analog-to-digital conversion system according to claim 5 , characterized in that the quantization noise E Q of the internal analog Δ-Σ loop herein acts as a perturbation signal to break the signal correlation characteristics due to low accuracy during MSB quantization, thereby eliminating the signal correlation spuriousness, and avoiding the problem that the error in the coarse quantization stage of the existing zoom Δ-Σ analog-to-digital conversion technique contains a large amount of spurious leakage.

7 . A low-latency MSB quantization method based on the nested Δ-Σ analog-to-digital conversion system of claim 1 , comprising a computer readable medium operable on a computer with memory for the low-latency MSB quantization method, and comprising program instructions for executing the following steps:
step 1: a digital filter filters the internal analog Δ-Σ loop output V to obtain the output signal D, and a first-in-first-out memory (FIFO) in the digital filter stores the data of the most recent H cycles of V, and the counter in the digital filter counts the H data in the FIFO, and the counting result D is the output of the digital filter;
step 2: a tri-state comparator in the MSB quantizer compares D to the thresholds D L , D H , and the tri-state comparator outputs +1 or −1 or no outputs;
step 3: an up-down accumulator accumulates the tri-state comparator output, and when the tri-state comparator output is +1, the up-down accumulator output is plus 1; when the tri-state comparator output is −1, the up-down accumulator output is minus 1; and when the tri-state comparator does not produce an output, the up-down accumulator output is unchanged;
each quantization changes only the data accumulated by the accumulator by +1 or −1 compared to the previous quantization of the MSB, and all the information of the MSB does not need to be derived in a single quantization of the MSB, but only the information of the lowest bit in the

Assignees

• Univ Shanghai Jiaotong

Inventors

• Guo yuekang
• Jin Jing
• Liu Xiaoming
• Zhou Jianjun

Classifications

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/49 Primary

  in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values · CPC title

• H03M3/458 Primary

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title