Apparatus for correcting linearity of a digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-9509326-B1
Application number	US-201514736155-A
Country	US
Kind code	B1
Filing date	Jun 10, 2015
Priority date	Jun 10, 2015
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

First claim

We claim:

1. An apparatus comprising:
a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and
measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.

2. The apparatus of claim 1 , wherein the DAC cell and the reference DAC cell are current steering DAC cells.

3. The apparatus of claim 2 , wherein the current steering DAC cells are differential current steering DAC cells.

4. The apparatus of claim 3 , wherein the differential current steering DAC cells are differential switched current steering DAC cells.

5. The apparatus of claim 1 , wherein the adjustable strength current source is a single current source for correcting the non-linearity of the DAC cell.

6. The apparatus of claim 1 , wherein the adjustable strength current source is an n-type current source coupled in parallel to the n-type current source of the DAC cell.

7. The apparatus of claim 1 , wherein the adjustable strength current source is a p-type current source coupled in parallel to the p-type current source of the DAC cell.

8. The apparatus of claim 1 , wherein the measurement circuit is operable to compare the p-type current source of the reference cell with the n-type current source of the DAC cell.

9. The apparatus of claim 1 , wherein the measurement circuit is operable to compare the n-type current source of the reference cell with the p-type current source of the DAC cell.

10. The apparatus of claim 1 further comprises logic to perform a dumping algorithm on the DAC cell.

11. The apparatus of claim 1 , wherein the DAC cell comprises:
a p-type switching cell coupled to the p-type current source of the DAC cell; and
an n-type switching cell coupled to the n-type current source of the DAC cell.

12. The apparatus of claim 11 , wherein the DAC cell further comprises a p-type transistor coupled in series with an n-type transistor, and wherein the p-type and n-type transistors are operable to electrically short the p-type current source to the n-type current source.

13. The apparatus of claim 12 , wherein the DAC cell further comprises a p-type transistor coupled in series with the p-type current source, and wherein the p-type transistor is operable to couple the n-type current source to the reference DAC cell.

14. The apparatus of claim 13 , wherein the DAC cell further comprises an n-type transistor coupled in series with the n-type current source, and wherein the n-type transistor is operable to couple the p-type current source to the reference DAC cell.

15. The apparatus of claim 1 comprises a switch for coupling the reference DAC cell with the DAC cell.

16. A sigma-delta modulator comprising:
an integrator to receive an input signal and to generate an output analog signal;
a analog-to-digital converter (ADC) to convert the output analog signal to a digital representation;
a digital-to-analog converter (DAC) to adjust the input signal, the DAC having a DAC cell having a single adjustable strength current source coupled to one of p-type or n-type current sources of the DAC cell; and
a measurement circuit to receive the digital representation and to control the single adjustable strength current source according to the digital representation, wherein the measurement circuit includes a reference DAC cell.

17. The sigma-delta modulator of claim 16 , wherein the measurement circuit is coupled to the DAC, and wherein the reference DAC cell includes p-type and n-type current sources.

18. The sigma-delta modulator of claim 16 , wherein the measurement circuit includes a multiplexer to select one of count-based or Successive Approximation Register (SAR)-based trimming method applicable to the single adjustable strength current source.

19. The sigma-delta modulator of claim 16 , wherein the single adjustable strength current source is operable to correct odd and even order harmonics.

20. The sigma-delta modulator of claim 16 comprises logic to perform a dumping algorithm to remove even order harmonics.

21. A system comprising:
an antenna;
a integrated circuit (IC) coupled to the antenna, the IC including:
a sigma-delta modulator comprising:
an integrator to receive an input signal and to generate an output analog signal;
a analog-to-digital converter (ADC) to convert the output analog signal to a digital representation;
a digital-to-analog converter (DAC) to adjust the input current, the DAC having a DAC cell having a single adjustable strength current source coupled to one of p-type or n-type current sources of the DAC cell; and
a measurement circuit to receive the digital representation and to control the single adjustable strength current source according to the digital representation; and

a processor coupled to the IC.

22. The system of claim 21 , wherein the measurement circuit is coupled to the DAC, and wherein the measurement circuit includes a reference DAC cell with p-type and n-type current sources.

Assignees

• Intel Ip Corp

Inventors

• Kauffman John G
• Schuetz Udo

Classifications

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/1004

  without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated (H03M1/1009, H03M1/1071 take precedence) · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title