Nanosheet transistor devices and related fabrication methods

Patent metadata

Field	Value
Publication number	US-12456647-B2
Application number	US-202217679465-A
Country	US
Kind code	B2
Filing date	Feb 24, 2022
Priority date	Dec 3, 2021
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

First claim

What is claimed is:

1. A method of forming a transistor device, the method comprising:
providing a sacrificial layer and a nanosheet stack on a substrate, wherein the sacrificial layer is between the nanosheet stack and the substrate, and wherein the nanosheet stack comprises a plurality of nanosheets;
removing the sacrificial layer to form an opening between the nanosheet stack and the substrate; and
forming a gate spacer and an isolation region by concurrently forming an insulating material on the nanosheet stack and in the opening, respectively.

2. The method of claim 1 ,
wherein the sacrificial layer is a bottom sacrificial layer,
wherein a plurality of upper sacrificial layers are alternately stacked with the nanosheets, and
wherein the bottom sacrificial layer has a higher germanium concentration than each of the upper sacrificial layers.

3. The method of claim 2 , further comprising replacing the upper sacrificial layers with a gate material after forming the gate spacer.

4. The method of claim 2 , wherein a semiconductor layer is between the bottom sacrificial layer and the upper sacrificial layers.

5. The method of claim 4 ,
wherein the semiconductor layer is configured to operate as a channel region, and
wherein the nanosheets are configured to operate as respective channel regions.

6. The method of claim 4 , wherein the semiconductor layer is configured to operate as a fully depleted silicon on insulator (FDSOI) channel region.

7. The method of claim 4 , further comprising forming the semiconductor layer by epitaxial growth from the bottom sacrificial layer.

8. The method of claim 7 , further comprising forming a plurality of source/drain regions by epitaxial growth from the semiconductor layer.

9. The method of claim 4 , wherein the semiconductor layer contacts the isolation region, after forming the gate spacer.

10. The method of claim 1 , wherein a buffer layer is between the sacrificial layer and the substrate.

11. The method of claim 10 , wherein the sacrificial layer has a higher germanium concentration than the buffer layer and is formed after forming the buffer layer.

12. A method of forming a transistor device, the method comprising:
providing a sacrificial layer and a nanosheet stack on a substrate, wherein the sacrificial layer is between the nanosheet stack and the substrate, and wherein the nanosheet stack comprises a plurality of nanosheets;
epitaxially growing a semiconductor layer from the sacrificial layer;
removing the sacrificial layer to form an opening between the semiconductor layer and the substrate; and
forming an isolation region by forming an insulating material in the opening.

13. The method of claim 12 , wherein the semiconductor layer is configured to operate as a fully depleted silicon on insulator (FDSOI) channel region.

14. The method of claim 13 , wherein the nanosheets are configured to operate as respective channel regions that are above the FDSOI channel region.

15. The method of claim 12 , further comprising forming a plurality of source/drain regions by epitaxial growth from the semiconductor layer.

16. The method of claim 12 , further comprising forming a gate material between the nanosheets,
wherein, after forming the gate material, a first surface of the semiconductor layer contacts the isolation region, and the gate material is on a second surface of the semiconductor layer, and
wherein a gate spacer is formed concurrently with the isolation region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• He Ming
• Park Jaehyun
• Ahn Chihak
• Saremi Mehdi
• Park Rebecca
• Simka Harsono
• Ha Daewon

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906 Primary

  Preparing SOI wafers · CPC title