Integrated circuit structure with backside via rail

Patent metadata

Field	Value
Publication number	US-11450751-B2
Application number	US-202117156584-A
Country	US
Kind code	B2
Filing date	Jan 24, 2021
Priority date	Jun 18, 2020
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface and a first sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.

First claim

What is claimed is:

1. An integrated circuit (IC) structure comprising:
a source epitaxial structure and a drain epitaxial structure;
a first silicide region on a front-side surface and a first sidewall of the source epitaxial structure;
a second silicide region on a front-side surface of the drain epitaxial structure;
a source contact in contact with the first silicide region and having a protrusion extending past a backside surface of the source epitaxial structure, wherein the protrusion of the source contact is spaced apart from the backside surface of the source epitaxial structure;
a backside via rail in contact with the protrusion of the source contact;
a drain contact in contact with the second silicide region; and
a front-side interconnection structure on a front-side surface of the source contact and a front-side surface of the drain contact.

2. The IC structure of claim 1 , wherein the first silicide region is thicker on the front-side surface of the source epitaxial structure than on the first sidewall of the source epitaxial structure.

3. The IC structure of claim 1 , wherein the first silicide region is further on a second sidewall of the source epitaxial structure opposite the first sidewall of the source epitaxial structure.

4. The IC structure of claim 3 , wherein the first silicide region is thicker on the front-side surface of the source epitaxial structure than on the second sidewall of the source epitaxial structure.

5. The IC structure of claim 1 , wherein the second silicide region is further on a first sidewall of the drain epitaxial structure.

6. The IC structure of claim 5 , wherein the second silicide region is absent from a second sidewall of the drain epitaxial structure opposite the first sidewall of the drain epitaxial structure.

7. The IC structure of claim 6 , further comprising:
a dielectric material in contact with the second sidewall of the drain epitaxial structure.

8. The IC structure of claim 1 , further comprising:
a dielectric cap separating the backside via rail from the drain contact.

9. The IC structure of claim 8 , wherein the protrusion of the source contact extends through the dielectric cap to the backside via rail.

10. The IC structure of claim 8 , further comprising:
a hybrid fin protruding from the dielectric cap toward the front-side interconnection structure.

11. The IC structure of claim 10 , wherein the hybrid fin has opposite sidewalls respectively in contact with the source contact and the drain contact.

12. The IC structure of claim 10 , wherein the hybrid fin comprises a liner layer and a fill oxide wrapped around by the liner layer.

13. An IC structure comprising:
a first transistor comprising a first source epitaxial structure, a first gate structure and a first drain epitaxial structure arranged along a first direction;
a second transistor comprising a second drain epitaxial structure, a second gate structure and a second source epitaxial structure arranged along the first direction;
a backside via rail extending along the first direction and arranged between the first transistor and the second transistor along a second direction substantially perpendicular to the first direction;
a source contact wrapping around a front-side surface and opposite sidewalls of the first source epitaxial structure from a cross-sectional view, the source contact extending past a backside surface of the first source epitaxial structure to the backside via rail from the cross-sectional view, wherein at least a part of the backside surface of the first source epitaxial structure non-overlaps the backside via rail; and
a drain contact extending along a first sidewall of the second drain epitaxial structure toward the backside via rail and terminating prior to reaching the backside via rail from the cross-sectional view.

14. The IC structure of claim 13 , further comprising:
a dielectric material in contact with a second sidewall of the second drain epitaxial structure opposite the first sidewall of the second drain epitaxial structure.

15. The IC structure of claim 13 , further comprising:
a silicide region on the second drain epitaxial structure, wherein the silicide region is thicker on a front-side surface of the second drain epitaxial structure than on the first sidewall of the second drain epitaxial structure from the cross-sectional view.

16. The IC structure of claim 13 , further comprising:
a silicide region wrapping around the front-side surface and the opposite sidewalls of the first source epitaxial structure and being wrapped around by the source contact from the cross-sectional view.

17. The IC structure of claim 16 , wherein the silicide region is thicker on the front-side surface of the first source epitaxial structure than on the opposite sidewalls of the first source epitaxial structure.

18. A method comprising:
forming a plurality of fins over a substrate;
forming a backside via rail between lower portions of the plurality of fins and a liner layer lining the backside via rail;
after forming the backside via rail, epitaxially growing a source epitaxial structure and a drain epitaxial structure on the plurality of fins;
performing a silicidation process to form a first silicide region on the source epitaxial structure and a second silicide region on the drain epitaxial structure;
after performing the silicidation process, forming a source contact in contact with the first silicide region and the backside via rail;
forming a front-side interconnection structure over the source contact;
removing the substrate and the liner layer to expose a backside surface of the backside via rail; and
forming a backside metal line extending laterally on the exposed backside surface of the backside via rail.

19. The method of claim 18 , wherein the source contact is formed to wrap around at least three sides of the source epitaxial structure.

20. The method of claim 18 , further comprising:
forming a hybrid fin between the plurality of fins; and
recessing partial regions of the plurality of fins, wherein the source epitaxial structure and the drain epitaxial structure are epitaxially grown on the recessed regions of the plurality of fins, and the source epitaxial structure and the drain epitaxial structure are on opposite sides of the hybrid fin and separated from the hybrid fin.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su Huan-Chieh
• Yu li-zhen
• Chen Chun-Yuan
• Chuang Cheng-Chi
• Chang Shang-Wen
• Chiu Yi-Hsun
• Wang Pei-Yu
• Tsai Ching-Wei
• Wang Chih-Hao

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/427

  Power or ground buses · CPC title