Nanowire structures having wrap-around contacts

Patent metadata

Field	Value
Publication number	US-10840366-B2
Application number	US-201916592380-A
Country	US
Kind code	B2
Filing date	Oct 3, 2019
Priority date	Dec 23, 2011
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising:
a discrete channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;
a pair of source or drain regions disposed in the nanowire, on either side of the channel region, each of the source or drain regions comprising a portion having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the portions of the source or drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the portions of the source or drain regions are immediately adjacent the channel region;

a gate electrode stack surrounding and in contact with the entire perimeter of each of the channel regions;
a pair of spacers adjacent the gate electrode stack; and
an intervening semiconductor material between and in contact with the plurality of vertically stacked nanowires but not along sidewalls of the nanowires at a location beneath the pair of spacers.

2. The semiconductor device of claim 1 , wherein each of the channel regions has a width and a height, the width approximately the same as the height, and wherein each of the portions of the source or drain regions has a width and a height, the width approximately the same as the height.

3. The semiconductor device of claim 1 , wherein each of the nanowires consists essentially of silicon, and the entire perimeter of each of the portions of the source or drain regions is an exposed <111> silicon surface.

4. The semiconductor device of claim 1 , wherein the gate electrode stack comprises a metal gate and a high-k gate dielectric, and each of the nanowires comprises silicon, germanium, or a combination thereof.

5. The semiconductor device of claim 1 , wherein each of the channel regions has a width and a height, the width substantially greater than the height, and wherein each of the portions of the source or drain regions has a width and a height, the width substantially greater than the height.

6. The semiconductor device of claim 5 , wherein each of the nanowires consists essentially of silicon, the perimeter along the width of each of the portions of the source or drain regions comprises exposed <110> silicon surfaces, and the perimeter along the height of each of the portions of the source or drain regions comprises exposed <100> silicon surfaces.

7. The semiconductor device of claim 1 , wherein each of the channel regions has a width and a height, the width substantially less than the height, and wherein each of the portions of the source or drain regions has a width and a height, the width substantially less than the height.

8. The semiconductor device of claim 7 , wherein each of the nanowires consists essentially of silicon, the perimeter along the width of each of the portions of the source or drain regions comprises exposed <100> silicon surfaces, and the perimeter along the height of each of the portions of the source or drain regions comprises exposed <110> silicon surfaces.

9. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising:
a discrete channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;
a pair of source or drain regions disposed in the nanowire, on either side of the channel region, each of the source or drain regions comprising a portion having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the portions of the source or drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the portions of the source or drain regions are immediately adjacent the channel region;

a gate electrode stack surrounding and in contact with the entire perimeter of each of the channel regions;
a pair of spacers adjacent the gate electrode stack; and
an intervening semiconductor material between and in contact with the plurality of vertically stacked nanowires but not along sidewalls of the nanowires at a location beneath the pair of spacers.

10. The computing device of claim 9 , further comprising:
a memory coupled to the board.

11. The computing device of claim 9 , further comprising:
a communication chip coupled to the board.

12. The computing device of claim 9 , further comprising:
a camera coupled to the board.

13. The computing device of claim 9 , further comprising:
a battery coupled to the board.

14. The computing device of claim 9 , further comprising:
an antenna coupled to the board.

15. The computing device of claim 9 , wherein the component is a packaged integrated circuit die.

16. The computing device of claim 9 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

17. The computing device of claim 9 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

18. The computing device of claim 9 , wherein each of the channel regions has a width and a height, the width approximately the same as the height, and wherein each of the portions of the source or drain regions has a width and a height, the width approximately the same as the height.

19. The computing device of claim 9 , wherein each of the channel regions has a width and a height, the width substantially greater than the height, and wherein each of the portions of the source or drain regions has a width and a height, the width substantially greater than the height.

20. The computing device of claim 9 , wherein the gate electrode stack comprises a metal gate and a high-k gate dielectric, and each of the nanowires comprises silicon, germanium, or a combination thereof.

Assignees

• Intel Corp

Inventors

• Cea Stephen M
• Weber Cory E
• Keys Patrick H
• Kim Seiyon
• Haverty Michael G
• Shankar Sadasivan

Classifications

• H10D30/0191

  forming stacked channels, e.g. changing their shapes or sizes · CPC title

• H10D30/502

  characterised by the stacked channels · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D62/121 Primary

  oriented parallel to substrates · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title