Distributed error detection and correction with hamming code handoff

Patent metadata

Field	Value
Publication number	US-12455784-B2
Application number	US-202217749921-A
Country	US
Kind code	B2
Filing date	May 20, 2022
Priority date	Oct 15, 2018
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

First claim

What is claimed is:

1. A device comprising:
a bus;
a memory access arbiter coupled to the bus, the memory access arbiter configured to:
receive a memory access request associated with a memory address;
generate a first error correction code associated with the memory access request; and
transmit the first error correction code on the bus; and

a plurality of components, including a data path manager, coupled to the bus, wherein each component of the plurality of components is configured to:
generate a first test error correction code associated with the memory access request;
compare the first test error correction code to the first error correction code to determine a number of bit errors associated with the first error correction code;
in response to the number of bit errors indicating more than one bit error, transmit an error code on the bus; and
in response to the number of bit errors indicating a single bit error, correct the single bit error.

2. The device of claim 1 , wherein:
the memory access request is a read memory access request; and
the first error correction code is an address Hamming code for the memory address of the read memory access request.

3. The device of claim 1 , wherein:
the memory access request is a write memory access request;
the memory access arbiter is further configured to:
generate a second error correction code based on data of the write memory access request; and
transmit on the bus the second error correction code with the data of the write memory access request; and

wherein each component of the plurality of components is further configured to:
generate a second test error correction code based on the data of the write memory access request;
compare the second test error correction code to the second error correction code to determine a number of bit errors associated with the second error correction code;
in response to the number of bit errors associated with the second error correction code indicating more than one bit error, transmit a second error code on the bus; and
in response to the number of bit errors associated with the second error correction code indicating a single bit error, correct the single bit error.

4. The device of claim 3 , wherein:
the first error correction code is an address Hamming code for the memory address of the write memory access request;
the second error correction code is a data Hamming code for the data of the write memory access request; and
the first error correction code and the second error correction code are each selected from one of an in band Hamming code and an out of band Hamming code.

5. The device of claim 1 , wherein:
the data path manager is further configured to output data associated with the memory access request.

6. The device of claim 1 , wherein:
the memory access arbiter is configured to arbitrate access to a cache and an external memory interleave circuit.

7. The device of claim 6 , wherein:
the plurality of components further includes the external memory interleave circuit;
the external memory interleave circuit is configured to arbitrate access to a first memory interface and a second memory interface; and
the plurality of components further includes the first memory interface and the second memory interface.

8. A method comprising:
receiving, by a memory access arbiter, a memory access request associated with data and a memory address;
generating, by the memory access arbiter, a first error correction code associated with the memory access request;
receiving, by a plurality of components that includes a data path manager, the first error correction code;
generating, by each component of the plurality of components, a first test error correction code associated with the memory access request;
comparing, by each component of the plurality of components, the first test error correction code to the first error correction code to determine a number of bit errors associated with the first error correction code;
in response to the number of bit errors indicating more than one bit error, transmitting, by each component of the plurality of components, an error code; and
in response to the number of bit errors indicating a single bit error, correcting, by each component of the plurality of components, the single bit error.

9. The method of claim 8 , wherein:
the memory access request is a read memory access request; and
the first error correction code is an address Hamming code for the memory address of the read memory access request.

10. The method of claim 8 , wherein:
the memory access request is a write memory access request; and wherein the method further comprises:
generating, by the memory access arbiter, a second error correction code based on data of the write memory access request;
transmitting, by the memory access arbiter, the second error correction code with the data of the write memory access request;
generating, by each component of the plurality of components, a second test error correction code based on the data of the write memory access request;
comparing, by each component of the plurality of components, the second test error correction code to the second error correction code to determine a number of bit errors associated with the second error correction code;
in response to the number of bit errors associated with the second error correction code indicating more than one bit error, transmitting, by each component of the plurality of components, a second error code; and
in response to the number of bit errors associated with the second error correction code indicating a single bit error, correcting, by each component of the plurality of components, the single bit error.

11. The method of claim 10 , wherein:
the first error correction code is an address Hamming code for the memory address of the write memory access request;
the second error correction code is a data Hamming code for the data of the write memory access request; and
the first error correction code and the second error correction code are each selected from one of an in band Hamming code and an out of band Hamming code.

12. The method of claim 8 , further comprising:
outputting, by the data path manager, data associated with the memory access request.

13. The method of claim 8 , further comprising:
arbitrating, by the memory access arbiter, access to a cache and an external memory interleave circuit.

14. The method of claim 13 , further comprising:
arbitrating, by the external memory interleave circuit, access to a first memory interface and a second memory interface.

15. A system comprising:
a bus;
a controller including a memory access arbiter configured to:
receive a write access request that includes an address and data;
generate an address error correction code;
generate a data error correction code; and
transmit the address error correction code, the data error correction code, and the data on the bus; and

a plurality of components, including a data path manager, coupled to the bus, wherein each component of the plurality of components is configured to:
generate a test address error correction code associated with the address of the write access request;
compare the test address error correction code to the address error correction code to determine a first number of bit errors associated with the address error correction code;
generate a test data error correction code associated with the data of the write access request;
compare the test data error correction code to the data error correction code to determine a second number of b

Assignees

• Texas Instruments Inc

Inventors

• Chirca Kai
• Wu Daniel
• Pierson Matthew David

Classifications

• G06F12/0862

  with prefetch · CPC title

• G06F12/0851

  Cache with interleaved addressing · CPC title

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F2212/6024

  History based prefetching · CPC title

• G06F2212/1048

  Scalability · CPC title